00001 #ifndef TGET4REC_H 00002 #define TGET4REC_H 00003 00004 00005 #include <vector> 00006 #include <stdint.h> 00007 00008 #include "TCBMBeamtimeProc.h" 00009 00010 #include "roc/Message.h" 00011 #include "roc/Board.h" 00012 #include "TRocEvent.h" 00013 #include "TRocParam.h" 00014 00015 #include "TGet4MessageFull.h" 00016 00017 class TRocParam; 00018 class TGo4MbsSubEvent; 00019 class TGet4MessageFull; 00020 00021 // Structure with all data field for 1 Get4 chip! 00022 struct TGet4Rec { 00023 // Synchronization check variables 00024 UInt_t uEpochMainClockSinceLastSync; // Main 250MHz clock epoch counter 00025 00026 UInt_t uLastEpoch2; // Last Epoch Nb from ROC message (global) 00027 UInt_t uRocEpochCycle; // Counter for the ROC epoch counter cycle (every 1048575 epochs) 00028 00029 ULong64_t uLocalEpochNb; // Last Epoch Nb from software count (local) 00030 UInt_t uLocalEpochCycle; // Counter for the ROC epoch counter cycle (every 1048575 epochs) 00031 00032 UInt_t uUnsyncedEpochs; 00033 UInt_t uUnsyncedEpochsSinceLastSync; 00034 00035 Char_t cAutomaticFakeSyncSinceLastSync; 00036 00037 UInt_t uModuloLastSynch; 00038 UInt_t uCycleLastSynch; 00039 00040 UInt_t u_nbConsLE[NB_CHAN_GET4]; 00041 UInt_t u_nbConsTE[NB_CHAN_GET4]; 00042 00043 Int_t iInterChipEpochShiftLast; 00044 00045 // Flags 00046 Bool_t bDataLossSinceLastSync; 00047 Bool_t bEpochLossSinceLastSync; 00048 Bool_t bFirstEpochBlock; 00049 std::vector<Bool_t> bValidEpochFlag; // 1 for each buffer 00050 Bool_t bChipGotASync; // Automatic GET4 chip failure detection 00051 Bool_t bStoredHitUnp; 00052 00053 // Get4 Reset Test 00054 Bool_t bJumpEpochBlockAfterReset; 00055 UInt_t uNbEpochBlockAfterReset; 00056 00057 // To survive missing events with a stream server 00058 Bool_t bFirstSyncAfterEventJump; 00059 00060 // buffer of hit messages for the current rpc epoch block to be build next 00061 // First vector size depends on the number of buffers used 00062 // (typical 3) 00063 std::vector< std::vector<TRocMessageExtended> > fCurrentEventMsg; 00064 // unsigned integer giving which buffer to use when 00065 // unpacking messages from a chip 00066 UInt_t uCurrentMessagesBuffer; 00067 std::vector<UInt_t> uEpochStart; // Start of each message XX epochs buffer 00068 std::vector<UInt_t> uCycleStart; // Start of each message XX epochs buffer 00069 00070 std::vector<Bool_t> bMessageInterBufferOk;// Boolean array indicating for each 00071 // buffer whether the Intermediate 00072 // messages buffer is ready for sorting 00073 // Intermediate event buffer for later splitting analysis 00074 UInt_t uCurrentMessageInterBuffer; 00075 00076 // buffer of not validated hit messages from previous MBS events which could match new trigger 00077 // after validation hit messages are put in the vector in the RocRec object 00078 std::vector< std::vector<TRocMessageExtended> > fCurrentUnprocessedMsg; 00079 // At the end of the event, messages accepted in trigger window but not validated are moved 00080 // in the output buffer to prevent data shifted because of buffering 00081 UInt_t uNotValidatedMessagesAccepted; 00082 00083 UInt_t u_messageCountLastEpoch; 00084 00085 // Histograms 00086 TH1 *fGet4RisEdgesNbEvol[NB_CHAN_GET4]; // Nb of rising edges depending on cycle/chan 00087 TH1 *fGet4FalEdgesNbEvol[NB_CHAN_GET4]; // Nb of falling edges depending on cycle/chan 00088 TH1 *fGet4HitsNbEvolution[NB_CHAN_GET4]; // Nb of matched hits depending on cycle/chan 00089 00090 TH1 *fGet4SyncSpacing; // Non synced Epochs between synced Epochs 00091 TH1 *fGet4SyncSpacingComp; // Non synced Epochs between synced Epochs, corrected for sync losses versus uncorrected 00092 TH1 *fGet4ValidEpochs; // Nb of valid Epochs (chips synched) for each chip 00093 TH1 *fGet4ValidSpacing; // Non synced Epochs between synced valid Epochs 00094 TH1 *fGet4InvalidSpacing; // Non synced Epochs between synced invalid Epochs 00095 TH1 *fGet4MessValidEpochs; // Nb of Messages in valid Epochs 00096 TH1 *fGet4AccMessNotValidated; // Nb of messages matching the trigger accepted without valid epoch bec. event end! 00097 00098 TH2 *fModuloSyncRoc; // Evolution of the modulo for the ROC epoch with sync 00099 TH2 *fModuloSyncLocal; // Evolution of the modulo for the local epoch with sync 00100 TH2 *fModuloSyncMainClock; // Evolution of the modulo for the 250MHz epoch with sync 00101 00102 TH2 *fInterChipSyncEpochShiftEvol; // Inter chip epoch shift check 00103 00104 // Debug! 00105 TH1 *fGet4FineTimeLE[NB_CHAN_GET4]; // Finetime of Leading Edge 00106 TH1 *fGet4FineTimeTE[NB_CHAN_GET4]; // Finetime of Trailing Edge 00107 TH1 *fGet4LeDnl[NB_CHAN_GET4]; // DNL value for each bin 00108 TH1 *fGet4LeDnlSum[NB_CHAN_GET4]; // Integral of DNL value up to each bin 00109 TH1 *fGet4TeDnl[NB_CHAN_GET4]; // DNL value for each bin 00110 TH1 *fGet4TeDnlSum[NB_CHAN_GET4]; // Integral of DNL value up to each bin 00111 TH1 *fNbConsecutiveLE[NB_CHAN_GET4]; // Nb of consecutive Leading edges (should stay at 1 or max 2 when multi hits) 00112 TH1 *fNbConsecutiveTE[NB_CHAN_GET4]; // Nb of consecutive Trailing edges (should stay at 1 or max 2 when multi hits) 00113 00114 TGet4Rec(); 00115 }; 00116 00117 #endif // TGET4REC_H
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