beamtime/cern-oct11/del_str/vulom3def.h (r4864/r1872)

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#define FLASHBASE   0x00c00000
#define FPGABASE    0x00000000
#define RANGE_REG   0x00800000
#define FPGA_DIRECT 0x00800004

#define DISPRAM     0x00010000
#define DISPREG     0x00020000
#define SRAM        0x00100000

#define PERIODREG   0x0
#define WIDTHREG    0x040
#define NPREG       0x080
#define ENABLEREG   0x0c0
#define SCALERREG       0x100
#define MODEREG         0x140

#define CSR_DONE    0x20
#define CSR_INIT    0x40

//#define CODE    0x0


/********************** DELAY &STRETCH ******************/
#define DS_ON_OFF   0x4         //turn channel on / off
#define DS_MOD      0x8         // modify cannel

/***************Delay Setup*****************************/
#define DS_DEL_1    0xc
#define DS_DEL_2    0x10
#define DS_DEL_3    0x14
#define DS_DEL_4    0x18
#define DS_DEL_5    0x1c
#define DS_DEL_6    0x20
#define DS_DEL_7    0x24
#define DS_DEL_8    0x28
#define DS_DEL_9    0x2c
#define DS_DEL_10   0x30
#define DS_DEL_11   0x34
#define DS_DEL_12   0x38
#define DS_DEL_13   0x3c
#define DS_DEL_14   0x40
#define DS_DEL_15   0x44
#define DS_DEL_16   0x48
#define DS_DEL_17   0x4c
#define DS_DEL_18   0x50
/***************Stretch Setup***************************/
#define DS_STR_1    0x54
#define DS_STR_2    0x58
#define DS_STR_3    0x5c
#define DS_STR_4    0x60
#define DS_STR_5    0x64
#define DS_STR_6    0x68
#define DS_STR_7    0x6c
#define DS_STR_8    0x70
#define DS_STR_9    0x74
#define DS_STR_10   0x78
#define DS_STR_11   0x7c
#define DS_STR_12   0x80
#define DS_STR_13   0x84
#define DS_STR_14   0x88
#define DS_STR_15   0x8c
#define DS_STR_16   0x90
#define DS_STR_17   0x94
#define DS_STR_18   0x98
/********************************************************/
#define N_SCALER        32



#define MAXBLOCK    63
#define BS  19