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beamtime/cern-oct12/vulom4/vulom3def.h (r4126/r1752)

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00001 
00002 #define FLASHBASE   0x00c00000
00003 #define FPGABASE    0x00000000
00004 #define RANGE_REG   0x00800000
00005 #define FPGA_DIRECT 0x00800004
00006 
00007 #define CSRREG      0x00000000
00008 #define DISPRAM     0x00010000
00009 #define DISPREG     0x00020000
00010 #define SRAM        0x00100000
00011 
00012 #define PERIODREG   0x0
00013 #define WIDTHREG    0x040
00014 #define NPREG       0x080
00015 #define ENABLEREG   0x0c0
00016 #define SCALERREG   0x100
00017 
00018 #define BS  19

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