Go to the documentation of this file.00001 #ifndef FLASH_ACCESS_H
00002 #define FLASH_ACCESS_H
00003
00004
00005
00006
00007
00008
00009 #define FA_VERBOSE 1
00010
00011
00012 #include "xparameters.h"
00013
00014
00015 #include "xbasic_types.h"
00016 #include "xutil.h"
00017
00018 #include <stdlib.h>
00019 #include <stdio.h>
00020 #include <string.h>
00021
00022
00023
00024
00025
00026 #define IDCODE_ADDR 0
00027
00028 #define CHECK_IDLE_ADDR 1
00029
00030 #define RESET_ADDR 2
00031
00032 #define GEN_WRITE_ADDR 3
00033
00034 #define DATA_READ_ADDR 4
00035
00036 #define DATA_WRITE_ADDR 5
00037
00038 #define ADDRESS_REG_ADDR 6
00039
00040 #define COMMAND_REG_ADDR 7
00041
00042 #define PCI_COMMAND_WRITE 2
00043 #define PCI_COMMAND_READ 4
00044
00045
00046
00047
00048
00049
00050
00051 #define FLASH_ACCESS_CMD_RESET 'a' //Send a to reset, repeat 100 a to force reset even if in Burst Mode
00052 #define FLASH_ACCESS_CMD_IDENT 'b' //Will Answer Ident String
00053 #define FLASH_ACCESS_CMD_READ 'c' //Send "c" [Addr] to read from Actel Addr
00054 #define FLASH_ACCESS_CMD_WRITE 'd' //Send "d" [Addr] [Byte2] [Byte1] [Byte0] to write 24 bit to Addr
00055 #define FLASH_ACCESS_CMD_TEST 'e' //Send to run test sequence
00056 #define FLASH_ACCESS_CMD_WRITE_BURST 'f' //Send "f", 4 byte Addr, 4 byte length, data
00057
00058
00059 #define FLASH_ACCESS_CMD_READ_BURST 'g' //Send "g", 4 byte Addr, 4 byte length, will require control byte "." every 4 bytes to ensure no fifo overflow
00060 #define FLASH_ACCESS_CMD_WRITE_ADDRESS 'h' //Write from Address to Flash, this is a direct PPC Address for example in DDR RAM Address Space
00061
00062
00063
00064 #define FLASH_ACCESS_CMD_PING 'p' //Should answer with pong 'p'
00065 #define FLASH_ACCESS_CMD_SET_DISABLE 'q' //Set Disable state for virtex_ok signal ('q' is nice for quit btfw :|)
00066
00067
00068 #define UART_STATE_IDLE 0
00069 #define UART_STATE_READ 1
00070 #define UART_STATE_WRITE 2
00071 #define UART_STATE_READ_BURST 3
00072 #define UART_STATE_WRITE_BURST 4
00073 #define UART_STATE_RESET 5
00074 #define UART_STATE_WRITE_ADDRESS 6
00075
00076 #define IDENT "PC to Network to Virtex to Actel to Flash Interface v1.0"
00077
00078 #define WRITE_BURST_CONTROL_INTERVAL 80
00079 #define READ_BURST_CONTROL_INTERVAL 16
00080
00081 #define VIRTEX_READ_TIMEOUT 100000
00082 #define FLASH_WAIT_TIME 100000
00083
00084 struct KibFileHeader
00085 {
00086 Xuint8 ident[4];
00087 Xuint32 headerSize;
00088 Xuint32 binfileSize;
00089 Xuint8 XORCheckSum;
00090 Xuint8 bitfileName[65];
00091 Xuint32 timestamp;
00092 };
00093
00094 int WaitVirtexReady();
00095 void TestSequence();
00096 int flash_access_send(Xuint8,Xuint8*);
00097 void flash_access_showBitfileInformation();
00098 Xuint8 flash_access_readByteFromFlashram(Xuint32 address);
00099 Xuint8 flash_access_checkIfChipErased(Xuint32 nChip);
00100 Xuint8 flash_access_writeByteToFlashram(Xuint32 address, Xuint8 data);
00101 void flash_access_chipErase(Xuint8 nChip);
00102 Xuint8 flash_access_flashBitfile(Xuint8* bitfile, Xuint8 positionNumber);
00103 void writeToFlashAccessModule(Xuint8 address, Xuint32 value);
00104 void writeDataToActel(Xuint32 address, Xuint32 value);
00105 Xuint32 readFromFlashAccessModule(Xuint8 address);
00106 void flash_access_copyBitfile();
00107 void flash_access_compareBitfiles();
00108 Xuint8 flash_access_calcXor();
00109 Xuint8 flash_access_calcKIBXor(int nChip);
00110
00111 #endif