beamtime/tof-tdctest/go4/MBSUNPACK/TMbsCrateEvent.h (r4864/r4267)

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#ifndef TMBSCRATEEVENT_H
#define TMBSCRATEEVENT_H

#include "TGo4EventElement.h"

#include "T1290Data.h"

#include <stdint.h>
/*
 * Put all definitions here and use them in processor,
 * since they are necessary for data structure of event
 */

#include "MbsCrateDefines.h"

class MQDC_t: public TObject {
  public:
     enum {NumChan = 16 };

     Int_t charge[NumChan];
     Int_t range[NumChan];
     Int_t under[NumChan];
     Int_t over[NumChan];

     MQDC_t() : TObject() { Clear(); };

     void Clear(void);

     void Unpack(int* pdata, unsigned len, int expected_geo = 0);

     static int FindGeo(int* pdata, int *len, int *crate);

   ClassDef(MQDC_t, 1)
};

struct FPGA_TDC_hit {
   uint32_t ch_ix;
   uint32_t coarse_ct;
   uint32_t ch_tim;
   uint32_t future_bit;
   // default constructor
   FPGA_TDC_hit() : ch_ix(0), coarse_ct(0), ch_tim(0), future_bit(0) {}

   // copy constructor, used by vector to copy content
   FPGA_TDC_hit(const FPGA_TDC_hit& src) :
      ch_ix(src.ch_ix), coarse_ct(src.coarse_ct), ch_tim(src.ch_tim), future_bit(src.future_bit) {}

   // Define < operator for vector sorting
   Bool_t operator <( const FPGA_TDC_hit& rhs) const
   {
      if( rhs.coarse_ct < VFTX_COARSE_OVERFLW_CHK &&
            this->coarse_ct >= rhs.coarse_ct + VFTX_COARSE_OVERFLW_CHK )
         // Corse counter overflow between this hit and checked one
         // hit ... Ovflw ... rhs
         return kTRUE;
      else if( this->coarse_ct < VFTX_COARSE_OVERFLW_CHK &&
            this->coarse_ct + VFTX_COARSE_OVERFLW_CHK <= rhs.coarse_ct )
         // Corse counter overflow between checked hit and this one
         // rhs ... Ovflw ... hit
         return kFALSE;
      else if( this->coarse_ct < rhs.coarse_ct )
         // CT hit ... rhs
         return kTRUE;
      else if( this->coarse_ct > rhs.coarse_ct )
         // CT rhs ... hit
         return kFALSE;
      else if( this->ch_tim > rhs.ch_tim)
         // Comparator inverted as FineTime is counting
         // Backward from next epoch!!!!!
         // CT rhs = hit
         // FT hit ... rhs
         return kTRUE;
      // CT rhs = hit
      // FT rhs ... hit or rhs = hit
      else return kFALSE;
   }
};


struct FPGA_TDC_header {
   uint32_t mod_nr;
   uint32_t nr_data;
   uint32_t fpga_fifo_tt;
   uint32_t fpga_fifo_ct;
   uint32_t fpga_fifo_nd;

   // default constructor
   FPGA_TDC_header() : mod_nr(0), nr_data(0), fpga_fifo_tt(0), fpga_fifo_ct(0), fpga_fifo_nd(0) {}

   // copy constructor, used by vector to copy content
   FPGA_TDC_header(const FPGA_TDC_header& src) :
      mod_nr(src.mod_nr), nr_data(src.nr_data), fpga_fifo_tt(src.fpga_fifo_tt), fpga_fifo_ct(src.fpga_fifo_ct), fpga_fifo_nd(src.fpga_fifo_nd) {}
};

struct QFW_Data {
   uint32_t counters[4];
   uint32_t errcnt[4];
   uint32_t setup;

   QFW_Data()
   {
      for (int n=0;n<4;n++) { counters[n] = 0; errcnt[n] = 0; }
      setup = 0;
   }

   QFW_Data(const QFW_Data& src)
   {
      for (int n=0;n<4;n++) {
         counters[n] = src.counters[n];
         errcnt[n] = src.errcnt[n];
      }
      setup = src.setup;
   }
};

struct ScalOrMu_Data {
   UInt_t uScaler[SCALORMU_NB_SCAL];
   UInt_t uReferenceClock;

   ScalOrMu_Data()
   {
      for( Int_t iScalerInd=0; iScalerInd < SCALORMU_NB_SCAL; iScalerInd++)
         uScaler[iScalerInd] = 0;
      uReferenceClock = 0;
   }

   ScalOrMu_Data(const ScalOrMu_Data& src)
   {
      for( Int_t iScalerInd=0; iScalerInd < SCALORMU_NB_SCAL; iScalerInd++)
         uScaler[iScalerInd] = src.uScaler[iScalerInd];
      uReferenceClock = src.uReferenceClock;
   }
};

class TMbsCrateEvent : public TGo4EventElement {

   public:

      TMbsCrateEvent();
      TMbsCrateEvent(const char* name, Short_t id=0);
      virtual ~TMbsCrateEvent();

      virtual void Clear(Option_t *t="");

      /* Data of 1182 QDC*/
      UShort_t fData1182[MAX_1182][NUM_1182_CH];

      T1290Data fMtdc[MAX_1290];

      MQDC_t fMqdc[MAX_965];

      std::vector<FPGA_TDC_hit>  fFPGA[MAX_FPGA_TDC];
      
      std::vector<FPGA_TDC_header> fFPGAHEAD[MAX_FPGA_TDC];

      QFW_Data fQFW;

      ScalOrMu_Data fScalOrMu;

      /* Triglog input pattern*/
      UInt_t fTriglogInputPattern;
      /* Internal 781250 Hz reference clock for rates calculation */
      UInt_t fTriglogReferenceClock;

   ClassDef(TMbsCrateEvent,3)
};

#endif //TEVENT_H