beamtime/gsi-aug12/get4v10/go4/MBSUNPACK/TMbsCrateEvent.h (r4864/r3846)

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#ifndef TMBSCRATEEVENT_H
#define TMBSCRATEEVENT_H

#include "TGo4EventElement.h"

#include "T1290Data.h"


#include <stdint.h>
/*
 * Put all definitions here and use them in processor,
 * since they are necessary for data structure of event
 */

// number of LeCroy 1182 modules
#define MAX_1182 2
// number of channels in LeCroy 1182 modules
#define NUM_1182_CH 8

// number of 1290 TDC modules
#define MAX_1290 8

// V1290 bin size
//#define CAENBINSIZE  25.0/1024.0

// number of 965 QDC Modules
#define MAX_965 3

// number of FPGA TDC modules
#define MAX_FPGA_TDC 11

//#define OLD_VERSION_VULOM // <- Pre-COSY nov11 HD vulom FPGA code
//#define VERSION_VFTX    // <- June   2012 version based on VFTX board (32 chan, 16 true chan+tot)
#define VERSION_VFTX_28 // <- August 2012 version based on VFTX board (56 chan, 28 true chan+tot)

// number of channels in FPGA TDC modules
#ifdef VERSION_VFTX
   #define FPGA_TDC_NBCHAN 32
#elif defined VERSION_VFTX_28
   #define FPGA_TDC_NBCHAN 56
#else
   #define FPGA_TDC_NBCHAN 8
#endif

/******************** FPGA TDC data unpacking definitions *************/
#define TDC_EVT_HEADER_KEY_MASK   0xFFFF0000
#define TDC_EVT_HEADER_KEY_SHIFT        16
#define TDC_EVT_HEADER_KEYWORD        0xABCD
#define TDC_EVT_HEADER_MOD_MASK   0x0000FF00
#define TDC_EVT_HEADER_MOD_SHIFT         8
#define TDC_EVT_HEADER_NB_MASK    0x000000FF


#ifdef OLD_VERSION_VULOM
   #define TDC_FIFO_FINE_CT          0x000003FF
   #define TDC_FIFO_COARSE_CT        0x01FFFC00 // Coarse counter value
   #define TDC_FIFO_COARSE_CT_SHIFT       10
   #define TDC_FIFO_COARSE_FT_SHIFT        0
   #define TDC_FIFO_FUTURE_BIT       0x02000000    // Flag for hits after trigger
   #define TDC_FIFO_FUTURE_BIT_SHIFT       25
   #define TDC_FIFO_DATA_CHAN        0x7C000000
   #define TDC_FIFO_DATA_CHAN_SHIFT        26
#elif defined VERSION_VFTX
   #define TDC_FIFO_FINE_CT          0x000007FF
   #define TDC_FIFO_COARSE_CT        0x01FFF800    // Coarse counter value
   #define TDC_FIFO_COARSE_CT_SHIFT        11
   #define TDC_FIFO_COARSE_FT_SHIFT        0
   #define TDC_FIFO_FUTURE_BIT       0x02000000    // Flag for hits after trigger
   #define TDC_FIFO_FUTURE_BIT_SHIFT       25
   #define TDC_FIFO_DATA_CHAN        0x7C000000    // Channel number
   #define TDC_FIFO_DATA_CHAN_SHIFT        26
#elif defined VERSION_VFTX_28
   #define TDC_FIFO_FINE_CT          0x000007FF
   #define TDC_FIFO_COARSE_CT        0x00FFF800    // Coarse counter value
   #define TDC_FIFO_COARSE_CT_SHIFT        11
   #define TDC_FIFO_COARSE_FT_SHIFT        0
   #define TDC_FIFO_FUTURE_BIT       0x01000000    // Flag for hits after trigger
   #define TDC_FIFO_FUTURE_BIT_SHIFT       24
   #define TDC_FIFO_DATA_CHAN        0x7E000000    // Channel number
   #define TDC_FIFO_DATA_CHAN_SHIFT        25
#else
   #define TDC_FIFO_FINE_CT          0x000007FF
   #define TDC_FIFO_COARSE_CT        0x03FFF800 // Coarse counter value
   #define TDC_FIFO_COARSE_CT_SHIFT       11
   #define TDC_FIFO_COARSE_FT_SHIFT        0
   #define TDC_FIFO_FUTURE_BIT       0x04000000    // Flag for hits after trigger
   #define TDC_FIFO_FUTURE_BIT_SHIFT       26
   #define TDC_FIFO_DATA_CHAN        0x78000000
   #define TDC_FIFO_DATA_CHAN_SHIFT        27
#endif

#ifdef OLD_VERSION_VULOM
   #define TDC_FIFO_HEADER_DATA_CNT  0x000000FF    // Data count
   #define TDC_FIFO_HEADER_TRIG_TIME 0x01FFFC00    // Coarse counter value
   #define TDC_FIFO_HEADER_TRIG_TIME_SHIFT  10
   #define TDC_FIFO_HEADER_TRIG_TYPE 0x60000000    // Trigger Type
   #define TDC_FIFO_HEADER_TRIG_TYPE_SHIFT 29
   #define TDC_FIFO_MESSAGE_TYPE     0x80000000    // Message Type 
   #define TDC_FIFO_MESSAGE_TYPE_SHIFT     31      // (1 = header, 0 = data)
#elif defined VERSION_VFTX
   #define TDC_FIFO_HEADER_DATA_CNT  0x000000FF    // Data count
   #define TDC_FIFO_HEADER_TRIG_TIME 0x01FFF800    // Coarse counter value
   #define TDC_FIFO_HEADER_TRIG_TIME_SHIFT  11
   #define TDC_FIFO_HEADER_TRIG_TYPE 0x60000000    // Trigger Type
   #define TDC_FIFO_HEADER_TRIG_TYPE_SHIFT 29
   #define TDC_FIFO_MESSAGE_TYPE     0x80000000    // Message Type 
   #define TDC_FIFO_MESSAGE_TYPE_SHIFT     31      // (1 = header, 0 = data)
#elif defined VERSION_VFTX_28
   #define TDC_FIFO_HEADER_DATA_CNT  0x000000FF    // Data count
   #define TDC_FIFO_HEADER_TRIG_TIME 0x00FFF800    // Coarse counter value
   #define TDC_FIFO_HEADER_TRIG_TIME_SHIFT  11
   #define TDC_FIFO_HEADER_TRIG_TYPE 0x60000000    // Trigger Type
   #define TDC_FIFO_HEADER_TRIG_TYPE_SHIFT 29
   #define TDC_FIFO_MESSAGE_TYPE     0x80000000    // Message Type 
   #define TDC_FIFO_MESSAGE_TYPE_SHIFT     31      // (1 = header, 0 = data)
#else
   #define TDC_FIFO_HEADER_DATA_CNT  0x000000FF    // Data count
   #define TDC_FIFO_HEADER_TRIG_TIME 0x03FFF800    // Coarse counter value
   #define TDC_FIFO_HEADER_TRIG_TIME_SHIFT  11
   #define TDC_FIFO_HEADER_TRIG_TYPE 0x60000000    // Trigger Type
   #define TDC_FIFO_HEADER_TRIG_TYPE_SHIFT 29
   #define TDC_FIFO_MESSAGE_TYPE     0x80000000    // Message Type 
   #define TDC_FIFO_MESSAGE_TYPE_SHIFT     31      // (1 = header, 0 = data)
#endif

/**************** End FPGA TDC data unpacking definitions *************/

// Number of scalers in ScalOrMu
   // Oct12
//#define SCALORMU_NB_SCAL    16
   // Nov 12
#define SCALORMU_NB_SCAL    24

class MQDC_t: public TObject {
  public:
     enum {NumChan = 16 };

     Int_t charge[NumChan];
     Int_t range[NumChan];
     Int_t under[NumChan];
     Int_t over[NumChan];

     MQDC_t() : TObject() { Clear(); };

     void Clear(void);

     void Unpack(int* pdata, unsigned len, int expected_geo = 0);

     static int FindGeo(int* pdata, int *len, int *crate);

   ClassDef(MQDC_t, 1)
};

struct FPGA_TDC_hit {
   uint32_t ch_ix;
   uint32_t coarse_ct;
   uint32_t ch_tim;
   uint32_t future_bit;
   // default constructor
   FPGA_TDC_hit() : ch_ix(0), coarse_ct(0), ch_tim(0), future_bit(0) {}

   // copy constructor, used by vector to copy content
   FPGA_TDC_hit(const FPGA_TDC_hit& src) :
      ch_ix(src.ch_ix), coarse_ct(src.coarse_ct), ch_tim(src.ch_tim), future_bit(src.future_bit) {}
};


struct FPGA_TDC_header {
   uint32_t mod_nr;
   uint32_t nr_data;
   uint32_t fpga_fifo_tt;
   uint32_t fpga_fifo_ct;
   uint32_t fpga_fifo_nd;

   // default constructor
   FPGA_TDC_header() : mod_nr(0), nr_data(0), fpga_fifo_tt(0), fpga_fifo_ct(0), fpga_fifo_nd(0) {}

   // copy constructor, used by vector to copy content
   FPGA_TDC_header(const FPGA_TDC_header& src) :
      mod_nr(src.mod_nr), nr_data(src.nr_data), fpga_fifo_tt(src.fpga_fifo_tt), fpga_fifo_ct(src.fpga_fifo_ct), fpga_fifo_nd(src.fpga_fifo_nd) {}
};

struct QFW_Data {
   uint32_t counters[4];
   uint32_t errcnt[4];
   uint32_t setup;

   QFW_Data()
   {
      for (int n=0;n<4;n++) { counters[n] = 0; errcnt[n] = 0; }
      setup = 0;
   }

   QFW_Data(const QFW_Data& src)
   {
      for (int n=0;n<4;n++) {
         counters[n] = src.counters[n];
         errcnt[n] = src.errcnt[n];
      }
      setup = src.setup;
   }
};

struct ScalOrMu_Data {
   UInt_t uScaler[SCALORMU_NB_SCAL];
   UInt_t uReferenceClock;

   ScalOrMu_Data()
   {
      for( Int_t iScalerInd=0; iScalerInd < SCALORMU_NB_SCAL; iScalerInd++)
         uScaler[iScalerInd] = 0;
      uReferenceClock = 0;
   }

   ScalOrMu_Data(const ScalOrMu_Data& src)
   {
      for( Int_t iScalerInd=0; iScalerInd < SCALORMU_NB_SCAL; iScalerInd++)
         uScaler[iScalerInd] = src.uScaler[iScalerInd];
      uReferenceClock = src.uReferenceClock;
   }
};

class TMbsCrateEvent : public TGo4EventElement {

   public:

      TMbsCrateEvent();
      TMbsCrateEvent(const char* name, Short_t id=0);
      virtual ~TMbsCrateEvent();

      virtual void Clear(Option_t *t="");

      /* Data of 1182 QDC*/
      UShort_t fData1182[MAX_1182][NUM_1182_CH];

      T1290Data fMtdc[MAX_1290];

      MQDC_t fMqdc[MAX_965];

      std::vector<FPGA_TDC_hit>  fFPGA[MAX_FPGA_TDC];
      
      std::vector<FPGA_TDC_header> fFPGAHEAD[MAX_FPGA_TDC];

      QFW_Data fQFW;

      ScalOrMu_Data fScalOrMu;

      /* Triglog input pattern*/
      UInt_t fTriglogInputPattern;
      /* Internal 781250 Hz reference clock for rates calculation */
      UInt_t fTriglogReferenceClock;

   ClassDef(TMbsCrateEvent,3)
};

#endif //TEVENT_H