ROCsoft: beamtime/gsi-aug12/get4v10/go4/VFTX/TVftxProc.cxx (r4864/r3846) Source File

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00001 #include "TVftxProc.h"
00002 #include "MBSUNPACK/TMbsCrateProc.h"
00003 
00004 #include "TTimeStamp.h"
00005 
00006 TVftxProc::TVftxProc(const char* name) : TCBMBeamtimeProc(name),fCrateInputEvent(0), fOutputEvent(0),fTriglogInputEvent(0)
00007 {
00008    TGo4Log::Info("**** TVftxProc: Create instance %s" , name );
00009 
00010    fPar = (TVftxParam*) MakeParameter("VftxPar", "TVftxParam");
00011 
00012    //~ cout<<name<<endl;
00013    iFirstModuleWithDiamond   = -1;
00014    iFirstModuleWithReference = -1;
00015    for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00016    { 
00017       if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00018       {
00019          fEventSizeHeader1[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader1_%d",imodule,imodule),
00020                      "Size of the event in event header", 256, -0.5, 255.5,"Size [words]");
00021          fEventSizeHeader2[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader2_%d",imodule,imodule),
00022                      "Size of the event in tdc header", 256, -0.5, 255.5,"Size [words]");
00023          fTriggerType[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerType%d",imodule,imodule),
00024                      "Trigger type in tdc header", 4, -0.5, 3.5,"Type []");
00025          fTriggerTime[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerTime%d",imodule,imodule),
00026                      "Time of the trigger in the coarse counter", 16383, 0, 16383,"Bin []");
00027                
00028          fChanUsage[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanUsage%d",imodule,imodule),
00029                    "Data on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00030          fChanEvents[imodule] = MakeTH1('I', Form("FPGA/ChanEvents%d",imodule),
00031                     "Data on channel during this event?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Events []");
00032                
00033          fChanFuture[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanFuture%d",imodule,imodule),
00034                     "Channel in future?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00035            
00036          fChanDouble[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanDouble%d",imodule,imodule),
00037                     "Double on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00038            
00039          fChanMultip[imodule] = MakeTH2('I', Form("FPGA/tdc%d/fChanMultip%d",imodule,imodule),
00040                     "Multiplicity per channel", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00041                     TVftxBoardData::MaxMult+1, 0, TVftxBoardData::MaxMult+1, "Channel []","Multiplicity []","Counts []");
00042 
00043          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00044          {
00045             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistEnable )
00046                fTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/time/chan%2dTime%d",imodule,ichan,imodule),
00047                       Form("Time to trigger Tdc %d channel %2d",imodule, ichan),
00048                       8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00049 
00050             if( 1 == fPar->uFineHistEnable )
00051             {
00052                TString sHistoName = Form("chan%2dFineTime%d",ichan,imodule);
00053                TString sHistoFullPath = Form("FPGA/tdc%d/ft/%s",imodule, sHistoName.Data() );
00054                TString sHistoTitle = Form("FineTime Tdc %d channel %2d",imodule, ichan);
00055                fFineTime[imodule][ichan] = MakeTH1('I', sHistoFullPath,
00056                      sHistoTitle,
00057                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00058                      "Fine Time [bin]");
00059                fFineTime[imodule][ichan]->Reset();
00060                TGo4Analysis::Instance()->ProtectObjects( sHistoName, "+C");
00061             }
00062 
00063             iNbHitsForCalib[imodule][ichan] = 0;
00064          }
00065          if( 1 == fPar->uFineEvolutionHistEnable )
00066             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00067             {
00068                fFineTimeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%2dFineTimeEvo%d",imodule,ichan,imodule),
00069                      Form("FineTime Tdc %d channel %2d",imodule, ichan),
00070                      72, -0.5, 72 - 0.5,
00071                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00072                      "Time [h]", "Fine Time [bin]");
00073                fBinSizeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%2dBinSizeEvo%d",imodule,ichan,imodule),
00074                      Form("Bin Size Tdc %d channel %2d",imodule, ichan),
00075                      200, -0.5, 1000- 0.5,
00076                      50, -0.5, 50 - 0.5,
00077                      "Time [min]", "Bin Size [ps]");
00078             }
00079       
00080       //histograms for the non-linear correction
00081          if( 1 == fPar->uEnableCalib )
00082          {
00083             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00084             {
00085                fDnlCorr[imodule][ichan] = MakeTH1('D', Form("FPGA/tdc%d/Dnl/chan%2dDnlCorr%d",imodule,ichan,imodule),
00086                          Form("DnlSum Tdc %d channel %2d",imodule, ichan),
00087                          TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00088                          "Fine Time [bin]");
00089             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00090 
00091             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTotHistoEnable )
00092                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN/2; ichan++)
00093                   fToT[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/tot/chan%2dToT%d",imodule,ichan,imodule),
00094                     Form("ToT Tdc %d channel %2d",imodule, ichan),
00095                     30000, -150000, 150000, "ToT [ps]");
00096          } // if( 1 == fPar->uEnableCalib )
00097       
00098          if( 1 == fPar->uBitControl)
00099          {
00100             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00101             {
00102                bitcontrol[imodule][ichan] = MakeTH1('I',
00103                          Form("FPGA/tdc%d/bits%d/chan%2dBitcontrol%d",imodule,imodule,ichan,imodule),
00104                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00105                          TDC_FIFO_COARSE_CT_SHIFT, 0, TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00106                bitcontrolCoarse[imodule][ichan] = MakeTH1('I',
00107                          Form("FPGA/tdc%d/bits%dCoarse/chan%2dBitcontrol%dCoarse",imodule,imodule,ichan,imodule),
00108                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00109                          TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,
00110                          0, TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00111             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00112          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl)
00113       
00114          if( 1 == fPar->uCoarseTimeHisto )
00115          {
00116             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00117             {
00118                fCoarseTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/ct/chan%2dCoarseTime%d",imodule,ichan,imodule),
00119                        Form("CoarseTime Tdc %d channel %2d",imodule, ichan),
00120                        TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT, -0.5, (TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT)-0.5,
00121                        "Coarse Time [bin]");
00122             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00123          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00124 
00125          // Checking how diamond time relatice to trigger depend on the triggers
00126          if( -1 < fPar->iVftxDiamondChannel[imodule] )
00127             fDiamondTimeTriggerDep[imodule] = MakeTH2('I', Form("FPGA/tdc%d/DiamondVsTrigger%d",imodule,imodule),
00128                   Form("Diamond Time to trigger depending on the active trigger, Tdc %d",imodule),
00129                   800, -395000, 5000, 16, 0, 16,
00130                   "Trigger time - Diamond Calibrated Time [ps]", "Trigger []");
00131 
00132          // Find first board with a diamond channel and then use it to compare the other boards
00133          if( -1 == iFirstModuleWithDiamond &&
00134                -1 < fPar->iVftxDiamondChannel[imodule])
00135             iFirstModuleWithDiamond = imodule;
00136          else if( -1 < fPar->iVftxDiamondChannel[imodule] && -1 < iFirstModuleWithDiamond)
00137             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithDiamond] &&
00138                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00139                fTdcResolutionDiamCheck[imodule - 1] = MakeTH1('I', Form("FPGA/DiamTdc%dVsTdc%d",imodule, iFirstModuleWithDiamond ),
00140                      Form("Diamond signal Tdc %d against Tdc %d",imodule, iFirstModuleWithDiamond),
00141                      30000, -15000, 15000,
00142                      Form("tDiamond%d - tDiamond%d [ps]", imodule, iFirstModuleWithDiamond));
00143 
00144          // Find first board with a reference channel and then use it to compare the other boards
00145          if( -1 == iFirstModuleWithReference &&
00146                -1 < fPar->iVftxReferenceChannel[imodule])
00147             iFirstModuleWithReference = imodule;
00148          else if( -1 < fPar->iVftxReferenceChannel[imodule])
00149             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference] &&
00150                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00151                fTdcResolutionRefCheck[imodule - 1] = MakeTH1('I', Form("FPGA/RefTdc%dVsTdc%d",imodule, iFirstModuleWithReference ),
00152                      Form("Time reference signal Tdc %d against Tdc %d",imodule, iFirstModuleWithReference),
00153                      30000, -15000, 15000,
00154                      Form("tRef%d - tRef%d [ps]", imodule, iFirstModuleWithReference));
00155       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00156    } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00157    uInitialMbsTime   = 0;
00158    uInitialVulomSync = 0;
00159 
00160    if( 1 == fPar->uVftxCoincidenceMap )
00161    {
00162       iMapIndex = 0;
00163       for( Int_t iModule1 = 0; iModule1 < MAX_FPGA_TDC; iModule1 ++)
00164          if( 1 == fPar->uVftxCalHistosEnabled[iModule1] )
00165             for( Int_t iModule2 = iModule1; iModule2 < MAX_FPGA_TDC; iModule2 ++)
00166             {
00167                if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00168                {
00169                   TGo4Log::Info("****Vftx monitor: Error creating mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00170                         iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule1, iModule2);
00171                   break;
00172                }
00173                if( 1 == fPar->uVftxCalHistosEnabled[iModule2] )
00174                   fTdcChanStripMapping[ iMapIndex ] =
00175                            MakeTH2('I', Form("FPGA/Mapping/Mapp%d_%dVftx", iModule1, iModule2 ),
00176                                         Form("Channel during same event?, Tdc %d VS Tdc %d", iModule1, iModule2),
00177                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00178                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00179                                          Form("Channel Tdc #%d []", iModule1),
00180                                          Form("Channel Tdc #%d []", iModule2),"Events []");
00181                iMapIndex++;
00182             }
00183    } // if( 1 == fPar->uVftxCoincidenceMap )
00184  
00185    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00186         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00187         1 == fPar->uEnableCalib )
00188    {
00189       TString sInitalCalibHistoName = "";
00190       fileCalibrationIn = new TFile( fPar->sInitialCalibrationFilename, "READ");
00191       
00192       if( kTRUE == fileCalibrationIn->IsOpen() )
00193       {
00194          TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00195          TGo4Log::Info("%s", sInfoLoading.Data() );
00196          sInfoLoading = "         ";
00197          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00198             sInfoLoading += Form("%2d ", ichan);
00199          TGo4Log::Info("%s", sInfoLoading.Data() );
00200 
00201          //define correction variables
00202          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00203          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00204 
00205          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00206          {
00207             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00208                continue;
00209 
00210             sInfoLoading = Form("tdc #%2d: ",imodule );
00211             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00212             {
00213                fInitialCalibHisto[imodule][ichan] = 0;
00214                sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00215                fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHisto[imodule][ichan]);
00216                
00217                if( 0 == fInitialCalibHisto[imodule][ichan] )
00218                   sInfoLoading += " 0 ";
00219                   else sInfoLoading += " 1 ";
00220 
00221                if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00222                {
00223                   // Try to use initial calibration histo always
00224                   fDnlCorr[imodule][ichan]->Reset();
00225                   //set a the sum to zero before summing over all bins in one channel
00226                   iSum[imodule][ichan] = 0;
00227                   Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00228 
00229                   for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00230                   {
00231                      Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00232                                          (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00233                      //Looking for the used bins
00234                      if( iBinContent <= 0)
00235                      {
00236                         bincontrol[ibin] = kFALSE;
00237                      }
00238                      else if( iBinContent > 0)
00239                      {
00240                         bincontrol[ibin] = kTRUE;
00241                      }
00242 
00243                      // build the sum of all bin content
00244                      if(bincontrol[ibin])
00245                      {
00246              iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00247              dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00248              if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable &&
00249                  2 == iNbHitsForCalib[imodule][ichan]%10000 )
00250                fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0,
00251                            CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00252                      }else
00253                      {
00254                         if( 0 < ibin)
00255                            dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00256                            else dCorr[imodule][ichan][ibin]=0;
00257                      }
00258                      fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00259                   } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00260                } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00261             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00262             TGo4Log::Info("%s", sInfoLoading.Data() );
00263          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00264       } // if( kTRUE == fileCalibrationIn->IsOpen() )
00265          else
00266          { 
00267             TGo4Log::Info("Could not open %s to load initial VFTX calibration, please check setting in Vftx_options.txt", 
00268                             fPar->sInitialCalibrationFilename.Data() );
00269             for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00270                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00271                   fInitialCalibHisto[imodule][ichan] = 0;
00272          } // else of if( kTRUE == fileCalibrationIn->IsOpen() )
00273 //      fileCalibrationIn->Close();
00274    } // if(  sInitialCalibrationFilename OK and 1 == fPar->uEnableCalib)
00275 
00276    //~ TGo4Log::Info("**** TVftxProc: Instance %s created", name );
00277 }
00278 
00279 
00280 TVftxProc::~TVftxProc()
00281 {
00282    cout << "**** TVftxProc: Delete instance " << endl;
00283    
00284    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00285         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00286         1 == fPar->uEnableCalib &&
00287         kTRUE == fileCalibrationIn->IsOpen() )
00288       fileCalibrationIn->Close();
00289       
00290    if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00291    {
00292       TTimeStamp timeCurrent;
00293       oldDir = gDirectory;
00294       TString sCalibOutFilename = Form("./VftxCalibHistos_%u_%u.root", timeCurrent.GetDate( kFALSE), timeCurrent.GetTime( kFALSE) );
00295       TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE", 
00296                                             Form("Calibration Data for VFTX, saved from analysis on %s", timeCurrent.AsString("lc") ), 
00297                                             9);
00298       if( kTRUE == fileCalibrationOut->IsOpen() )
00299       {
00300          sCalibOutFilename += ":/";
00301          gDirectory->Cd(sCalibOutFilename);
00302          TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00303          TGo4Log::Info("%s", sInfoSaving.Data() );
00304          sInfoSaving = "         ";
00305          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00306             sInfoSaving += Form("%2d ", ichan);
00307          TGo4Log::Info("%s", sInfoSaving.Data() );
00308          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00309          {
00310             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00311                continue;
00312             sInfoSaving = Form("tdc #%2d: ",imodule );
00313             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00314             {
00315                if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00316                {
00317                fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00318                                                  TObject::kOverwrite);
00319                sInfoSaving += " 1 ";
00320                }
00321                   else sInfoSaving += " 0 ";
00322             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00323             TGo4Log::Info("%s", sInfoSaving.Data() );
00324          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00325          //fileCalibrationOut->Write("",TObject::kOverwrite);
00326          fileCalibrationOut->Close();
00327          TGo4Log::Info("Calibration data saved in %s", sCalibOutFilename.Data() );
00328       } // if( kTRUE == fileCalibrationOut->IsOpen() )
00329          else TGo4Log::Warn("Error when deleting TVftxProc: Unable to open root file %s to save calibration data, please check settings",
00330                               sCalibOutFilename.Data() );
00331       gDirectory->Cd(oldDir->GetPath());
00332    } // if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00333 }
00334 
00335 void TVftxProc::InitEvent(TGo4EventElement* outevnt)
00336 {
00337    // first assign input event:
00338    // since input event object is never discarded within processor lifetime,
00339    // we just search for subevent by name once to speed up processing
00340 
00341    //cout << "VftxProc Init Event " <<  endl;
00342 
00343    if(fCrateInputEvent==0)
00344    {
00345       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(GetInputEvent());
00346       if(btevent)
00347       {
00348          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(btevent->GetSubEvent("MBSCRATE"));
00349          fTriglogInputEvent=dynamic_cast<TTriglogEvent*>(btevent->GetSubEvent("TRIGLOG"));
00350       }
00351       else
00352       {
00353          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(GetInputEvent());
00354       }
00355       if(fCrateInputEvent==0) {
00356         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event is not a TMbsCrateEvent!!! STOP GO4");
00357       }
00358       if(fTriglogInputEvent==0) {
00359         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event has no TTriglogEvent!!! STOP GO4");
00360       }
00361    }
00362    // then assign output event
00363 
00364    // since output event object is never discarded within processor lifetime,
00365    // we just search for subevent by name once to speed up processing
00366    if(fOutputEvent==0)
00367    {
00368       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(outevnt);
00369       if(btevent)
00370       {
00371          fOutputEvent=dynamic_cast<TVftxEvent*>(btevent->GetSubEvent("VFTX"));
00372       }
00373       else
00374       {
00375 
00376          fOutputEvent= dynamic_cast<TVftxEvent*>(outevnt);
00377       }
00378       if(fOutputEvent==0) {
00379         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: output event is not a TVftxEvent!!! STOP GO4");
00380       }
00381       else {
00382          //     BuildEvent(dynamic_cast<TGo4MbsSubEvent*>(btevent->GetSubEvent("MBSCRATE")));
00383       }
00384    }
00385 }
00386 
00387 void TVftxProc::FinalizeEvent()
00388 {
00389   //   cout << "**** TVftxProc: Finalize Event " << endl;
00390    if (fCrateInputEvent->IsValid()) 
00391    {
00392       // variables
00393       Int_t imodule = 0;
00394       Int_t iEvtSizeHeader1[MAX_FPGA_TDC];
00395       Int_t iEvtSizeHeader2[MAX_FPGA_TDC];
00396       for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++) 
00397       {
00398          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00399          {
00400             iFirstTime[imodule][ichan]     = -1;
00401             iFirstCoarse[imodule][ichan]   = -1;
00402             iFirstFine[imodule][ichan]     = -1;
00403             dFirstTimecorr[imodule][ichan] = -1;
00404             dFirstFineTimecorr[imodule][ichan] = -1;
00405             iLastTime[imodule][ichan]    = 0;
00406             for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00407             {
00408                dTimeCorr[imodule][ichan][imul] = -1;
00409                dFineTimeCorr[imodule][ichan][imul] = -1;
00410             }
00411             uTotalMultiplicity[imodule][ichan]    = 0;
00412          }
00413          iTriggerTime[imodule] = 0;
00414       }
00415       imodule = 0;
00416       // fill histograms    
00417       for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++) {
00418          if( 0 == fPar->uVftxCalHistosEnabled[fpga] )
00419             continue;
00420 
00421          unsigned num_hits = fCrateInputEvent->fFPGA[fpga].size(); // per tdc
00422          imodule  = fpga;
00423          
00424          if( 0 == num_hits && 0 == fCrateInputEvent->fFPGAHEAD[fpga].size() ) // check if fpga data are there
00425             continue;
00426          iEvtSizeHeader1[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).nr_data;
00427          iEvtSizeHeader2[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_nd;
00428          iTriggerTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00429          headTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00430          
00431          if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00432          {
00433             fEventSizeHeader1[imodule]->Fill( iEvtSizeHeader1[imodule] );
00434             fEventSizeHeader2[imodule]->Fill( iEvtSizeHeader2[imodule] );
00435             fTriggerType[imodule]->Fill(fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_tt);
00436             fTriggerTime[imodule]->Fill( iTriggerTime[imodule] );
00437          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00438          
00439          (fOutputEvent->fVftxBoards[imodule]).iTriggerTime = headTime[imodule];
00440          
00441          for(unsigned i = 0; i<num_hits; i++) 
00442          {
00443             uint32_t ichan =  fCrateInputEvent->fFPGA[fpga].at(i).ch_ix;
00444             uint32_t bFutureBit = fCrateInputEvent->fFPGA[fpga].at(i).future_bit;
00445             int32_t iCoarseCounter =  fCrateInputEvent->fFPGA[fpga].at(i).coarse_ct;
00446             int32_t iFineCounter =  fCrateInputEvent->fFPGA[fpga].at(i).ch_tim;
00447 
00448             // for given module add data
00449             Int_t channel=ichan; 
00450                
00451             if( (imodule >= 0) && (imodule < MAX_FPGA_TDC) && 
00452                 (channel >= 0) && (channel < FPGA_TDC_NBCHAN) )
00453             {
00454 
00455                if( ((fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] < TVftxBoardData::TVftxBoardData::MaxMult) )
00456                {
00457                   (fOutputEvent->fVftxBoards[imodule]).iFineTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]   = iFineCounter;
00458                   (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ] = iCoarseCounter;
00459                   (fOutputEvent->fVftxBoards[imodule]).uFutureBit[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]  = bFutureBit;
00460                   (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel]++;
00461                }
00462                uTotalMultiplicity[imodule][channel]++;
00463             }
00464                else continue;
00465 
00466             //Calculation of non-linear Correction
00467             if( 0 == uInitialMbsTime )
00468             {
00469                uInitialMbsTime   = fTriglogInputEvent->fMbsTimeSecs;
00470                uInitialVulomSync = fTriglogInputEvent->fVulomSyncNumber;
00471             }
00472             if( 1 == fPar->uFineHistEnable )
00473             {
00474                if( 0 == fFineTime[imodule][ichan]->GetEntries() )
00475                   iNbHitsForCalib[imodule][ichan] = 0;
00476                   
00477                fFineTime[imodule][ichan]->Fill(iFineCounter);
00478                
00479                iNbHitsForCalib[imodule][ichan] ++;
00480                if( fPar->iMinNbHitsCalib == iNbHitsForCalib[imodule][ichan] )
00481                   TGo4Log::Info("FPGA TDC: Calibration data ok for module %d channel %d, after %d events", imodule, ichan, fTriglogInputEvent->fVulomSyncNumber - uInitialVulomSync);
00482             }
00483             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable )
00484                fFineTimeEvo[imodule][ichan]->Fill( UInt_t((fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/3600), iFineCounter);
00485 
00486             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00487                fCoarseTime[imodule][ichan]->Fill(iCoarseCounter);
00488 
00489             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00490             {
00491                for (uint16_t ibit = 0; ibit <= 9; ibit++) 
00492                   if ((iFineCounter >> ibit) & 0x1) bitcontrol[imodule][ichan]->Fill( ibit );
00493                for (uint16_t ibit = 0; ibit <= 15; ibit++) 
00494                   if ((iCoarseCounter >> ibit) & 0x1) bitcontrolCoarse[imodule][ichan]->Fill( ibit );
00495             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00496 
00497             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00498             {
00499                fChanUsage[imodule]->Fill(ichan);
00500                if (bFutureBit) fChanFuture[imodule]->Fill(ichan);
00501             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00502 
00503             if (iLastTime[imodule][ichan])
00504             {
00505                if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00506                   fChanDouble[imodule]->Fill(ichan);
00507             }
00508             else
00509             {
00510                iFirstCoarse[imodule][ichan] = iCoarseCounter;
00511                iFirstFine[imodule][ichan]   = iFineCounter;
00512                iFirstTime[imodule][ichan]   = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)
00513                                                + iFineCounter; // Modif PAL to re-add the coarse counter shift
00514             }
00515 
00516             iLastTime[imodule][ichan] = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)  + iFineCounter;
00517          } // for(unsigned i = 0; i<num_hits; i++)
00518             
00519       } // for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++)
00520       
00521       if( 1 == fPar->uEnableCalib )
00522       {
00523          //define correction variables
00524          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00525          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00526         
00527          for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00528          {
00529             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00530                continue;
00531 
00532             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00533             {
00534                // cout<<" Test Corr Tdc "<<imodule<<" chan "<<ichan<<endl;
00535                if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]  &&
00536                    -1 <  fPar->iMinNbHitsCalib)
00537                {
00538                   if(// iNbHitsForCalib[imodule][ichan]< (2*fPar->iMinNbHitsCalib) ||
00539                     0 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00540                   {
00541                      fDnlCorr[imodule][ichan]->Reset();
00542                      //set a the sum to zero before summing over all bins in one channel
00543                      iSum[imodule][ichan] = 0;
00544                      Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() );
00545                      
00546                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00547                      {
00548                         Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1));
00549                         //Looking for the used bins
00550                         if( iBinContent <= 0)
00551                         {
00552                            bincontrol[ibin] = kFALSE;
00553                         }
00554                         else if( iBinContent > 0)
00555                         {
00556                            bincontrol[ibin] = kTRUE;
00557                         }
00558                            
00559                         // build the sum of all bin content
00560                         if(bincontrol[ibin])
00561                         {
00562                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00563                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00564                 if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00565                     0 == iNbHitsForCalib[imodule][ichan]%10000 )
00566                   fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00567                               CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00568                         }else
00569                         {
00570                            if( 0 < ibin)
00571                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00572                               else dCorr[imodule][ichan][ibin]=0;
00573                         }      
00574                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00575                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00576                   } // if( iNbHitsForCalib[imodule][ichan]<1e6 || 0 == iNbHitsForCalib[imodule][ichan]%40000 )
00577                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00578                   else if( -1 < fPar->iMinNbHitsCalib )
00579                   {
00580                      // Try to use initial calibration histo as long as under 
00581                      // the minimal number of hits in calibration
00582                      if( 0 != fInitialCalibHisto[imodule][ichan] &&
00583                          2 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00584                      {
00585                         fDnlCorr[imodule][ichan]->Reset();
00586                         //set a the sum to zero before summing over all bins in one channel
00587                         iSum[imodule][ichan] = 0;
00588                         Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() ) + 
00589                                                         (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00590                         
00591                         for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00592                         {
00593                            Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00594                                                (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00595                            //Looking for the used bins
00596                            if( iBinContent <= 0)
00597                            {
00598                               bincontrol[ibin] = kFALSE;
00599                            }
00600                            else if( iBinContent > 0)
00601                            {
00602                               bincontrol[ibin] = kTRUE;
00603                            }
00604                               
00605                            // build the sum of all bin content
00606                            if(bincontrol[ibin])
00607                            {
00608                    iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00609                    dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00610                    if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00611                        2 == iNbHitsForCalib[imodule][ichan]%10000 )
00612                      fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00613                                  CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00614                            }else
00615                            {
00616                               if( 0 < ibin)
00617                                  dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00618                                  else dCorr[imodule][ichan][ibin]=0;
00619                            }      
00620                            fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00621                         } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00622                      } //  if( 0 != fInitialCalibHisto[imodule][ichan] )
00623                   } // else of else if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00624                
00625                if( ( -1<fPar->iMinNbHitsCalib && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]) ||
00626                    0 != fInitialCalibHisto[imodule][ichan] )
00627                {
00628                   if( 0<=iFirstCoarse[imodule][ichan] || 0<=iFirstFine[imodule][ichan] )
00629                   {
00630           dFirstTimecorr[imodule][ichan] = iFirstCoarse[imodule][ichan]*CLOCK_TIME
00631                    +  (1 - dCorr[imodule][ichan][iFirstFine[imodule][ichan]])*CLOCK_TIME;
00632                    dFirstFineTimecorr[imodule][ichan] = dCorr[imodule][ichan][iFirstFine[imodule][ichan]]*CLOCK_TIME;  
00633                   }  
00634                   for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00635                      if( 0<=(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul] || 
00636                          0<=(fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul])
00637                      {
00638                         dTimeCorr[imodule][ichan][imul] = (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul]*CLOCK_TIME
00639                             +  (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME; 
00640                         dFineTimeCorr[imodule][ichan][imul] = (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME;
00641                         
00642                         // Fill it in output event
00643                         (fOutputEvent->fVftxBoards[imodule]).dTimeCorr[ichan][imul]     = dTimeCorr[imodule][ichan][imul];
00644                         (fOutputEvent->fVftxBoards[imodule]).dFineTimeCorr[ichan][imul] = dFineTimeCorr[imodule][ichan][imul];
00645                      } // if( iFineTime ok || iCoarseTime ok)
00646                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])
00647                
00648             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00649                
00650             //Compare corrected time with trigger time 
00651             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00652             {
00653 #if defined(VERSION_VFTX) || defined(VERSION_VFTX_28) // 1 TDC mode, chan = Time, chan +1 = Tot
00654                /*
00655                Double_t dTimeToTrigger[FPGA_TDC_NBCHAN];
00656                Double_t dToT[FPGA_TDC_NBCHAN];
00657                for( Int_t ichan = 0; ichan < FPGA_TDC_NBCHAN; ichan ++)
00658                {
00659                   if( 1 == fPar->uTimeHistEnable && 
00660                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])&&
00661                       0 < iFirstTime[imodule][ichan] )
00662                   {
00663                      dTimeToTrigger[ichan] = dFirstTimecorr[imodule][ichan] - iTriggerTime[imodule]*CLOCK_TIME;
00664                      if( 1000 < iFirstCoarse[imodule][ichan] - iTriggerTime[imodule])
00665                         dTimeToTrigger[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00666                      if( iFirstCoarse[imodule][ichan] - iTriggerTime[imodule] < -1000 )
00667                         dTimeToTrigger[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00668                      fTime[imodule][ichan]->Fill( dTimeToTrigger[ichan] );
00669                   }
00670                   if( 1 == fPar->uTotHistoEnable && ichan < FPGA_TDC_NBCHAN/2 )
00671                      if( 0 < iFirstTime[imodule][ichan*2] && 0 < iFirstTime[imodule][ichan*2+1] &&
00672                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2]   || 0 != fInitialCalibHisto[imodule][ichan*2]  )&&
00673                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2+1] || 0 != fInitialCalibHisto[imodule][ichan*2+1]) )
00674                      {
00675                         dToT[ichan] =  dFirstTimecorr[imodule][ichan*2] -  dFirstTimecorr[imodule][ichan*2+1] ;
00676                         if( 1000 < iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] )
00677                            dToT[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00678                         if( iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] < -1000 )
00679                            dToT[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00680                         fToT[imodule][ichan]->Fill(dToT[ichan]);
00681                      } // if( 1 == fPar->uTotHistoEnable && .... )
00682                }
00683                */
00684 #else
00685                if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][0])
00686                   fTime[imodule][0]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME - dFirstTimecorr[imodule][0]);
00687                if( 1 == fPar->uTotHistoEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0]
00688                   && fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00689                   fToT[0]->Fill(((Double_t)iTriggerTime[0]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[0][0] 
00690                              - (((Double_t)iTriggerTime[1]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[1][0]));
00691                Double_t dToT[FPGA_TDC_NBCHAN];
00692                for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00693                {
00694                   if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00695                      fTime[imodule][ichan]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME
00696                                                   - dFirstTimecorr[imodule][ichan]);
00697                   if( 1 == fPar->uTotHistoEnable && 
00698                       0 < iFirstTime[0][ichan] && 0 < iFirstTime[1][ichan] &&
00699                       0 < iFirstTime[0][0]     && 0 < iFirstTime[1][0]  && 
00700                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00701                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][1] &&
00702                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00703                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00704                   {
00705                       dToT[ichan] = (iTriggerTime[0]*(Double_t)CLOCK_TIME )  - dFirstTimecorr[0][ichan] 
00706                         - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][ichan])
00707                         - ( (iTriggerTime[0]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[0][0] 
00708                        - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][0])) ;
00709                      fToT[ichan]->Fill(dToT[ichan]);
00710                   } // if( 1 == fPar->uTotHistoEnable && .... )
00711                } // for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00712 #endif
00713             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00714          } // for(  imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00715 
00716          // Fill the output event
00717          for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
00718          {
00719             if( 0 == fPar->uVftxCalHistosEnabled[iModule] )
00720                continue;
00721 
00722             Double_t dTimeToTrigger;
00723             Double_t dToT;
00724             for(Int_t iChan=0; iChan < FPGA_TDC_NBCHAN; iChan++)
00725             {
00726                for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
00727                {
00728                   if( 1 == fPar->uTimeHistEnable &&
00729                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan] || 0 != fInitialCalibHisto[iModule][iChan])&&
00730                       0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]  )
00731                   {
00732                      dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
00733                                      - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
00734                      if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
00735                         dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00736                      if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1000 )
00737                         dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00738                      fTime[iModule][iChan]->Fill( dTimeToTrigger );
00739                   } // if hit is ok and calibrated
00740                } // for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
00741                if( 1 == fPar->uTotHistoEnable && iChan < FPGA_TDC_NBCHAN/2 )
00742                   for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2 ] &&
00743                                        iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2+1 ]; iHit++)
00744                   {
00745                      if( 0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit] &&
00746                            0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit] &&
00747                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2]   || 0 != fInitialCalibHisto[iModule][iChan*2]  )&&
00748                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2+1] || 0 != fInitialCalibHisto[iModule][iChan*2+1]) )
00749                      {
00750                         dToT =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit]
00751                                      -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit];
00752                         if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
00753                                    - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] )
00754                            dToT -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00755                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
00756                             - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] < -1000 )
00757                            dToT += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00758                         fToT[iModule][iChan]->Fill(dToT);
00759                      } // if both edges ok and calibrated
00760                   } // for all hits until one edge is missing
00761 
00762                // Go back to index for VFTX internal map
00763                if( 1 == fPar->uVftxCoincidenceMap )
00764                   iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
00765                            - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2;
00766 
00767                if( 1 == fPar->uVftxCalHistosEnabled[iModule]  &&
00768                    0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan] )
00769                {
00770                   fChanEvents[iModule]->Fill(iChan);
00771                   if( 1 == fPar->uVftxCoincidenceMap )
00772                   {
00773                      if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00774                      {
00775                         TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00776                               iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule);
00777                         return;
00778                      } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00779                      for(Int_t iChan2=iChan+1; iChan2<FPGA_TDC_NBCHAN; iChan2++)
00780                         if( 1 == fPar->uVftxCalHistosEnabled[iModule] && 0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan2] )
00781                         {
00782                            fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
00783                         }
00784 
00785                      for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
00786                      {
00787                         // Find index for corresponding VFTX against VFTX map
00788                         iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
00789                                  - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2
00790                                  + (iModule2 - iModule);
00791                         if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00792                         {
00793                            TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00794                                  iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule2);
00795                            return;
00796                         } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00797                         for(Int_t iChan2=0; iChan2<FPGA_TDC_NBCHAN; iChan2++)
00798                            if( 1 == fPar->uVftxCalHistosEnabled[iModule2] && 0<(fOutputEvent->fVftxBoards[iModule2]).iMultiplicity[iChan2] )
00799                            {
00800                               fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
00801                            }
00802                      } // for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
00803                   } // if( 1 == fPar->uVftxCoincidenceMap )
00804                } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && chan1 there)
00805 
00806                if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
00807                   fChanMultip[iModule]->Fill(iChan, uTotalMultiplicity[iModule][iChan] );
00808             } // for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++)
00809          } //  for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
00810 
00811          // Checking how diamond time relatice to trigger depend on the triggers
00812          Double_t dDiamondTimeToTrigger = 0.0;
00813          for(Int_t iTrigger = 0; iTrigger<16; iTrigger++)
00814             if( 1 == ((fTriglogInputEvent->fVulomTriggerPattern>>iTrigger) & 0x1) )
00815                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
00816                   if( -1 < fPar->iVftxDiamondChannel[iModule] )
00817                      for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxDiamondChannel[iModule] ]; iHit++)
00818                {
00819                   dDiamondTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxDiamondChannel[iModule]][iHit]
00820                                           - iTriggerTime[iModule]*CLOCK_TIME;
00821                   if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxDiamondChannel[iModule]][iHit] - iTriggerTime[iModule])
00822                      dDiamondTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00823                   if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxDiamondChannel[iModule]][iHit] - iTriggerTime[iModule] < -1000 )
00824                      dDiamondTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00825                   fDiamondTimeTriggerDep[iModule]->Fill( dDiamondTimeToTrigger, iTrigger );
00826                } //  for Trigger, Module, Hit, if Trigger there and Diamond channel of the module defined
00827 
00828          if( -1 < iFirstModuleWithDiamond)
00829             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithDiamond] &&
00830                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithDiamond]).iMultiplicity[fPar->iVftxDiamondChannel[iFirstModuleWithDiamond]] )
00831                for(Int_t iModule=1; iModule<MAX_FPGA_TDC; iModule++)
00832                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] && fPar->iVftxDiamondChannel[iModule] )
00833                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxDiamondChannel[iModule]] )
00834                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxDiamondChannel[iModule]][0] &&
00835                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithDiamond]).dTimeCorr[fPar->iVftxDiamondChannel[iFirstModuleWithDiamond]][0] )
00836                      fTdcResolutionDiamCheck[iModule-1]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxDiamondChannel[iModule]][0] -
00837                                 (fOutputEvent->fVftxBoards[iFirstModuleWithDiamond]).dTimeCorr[fPar->iVftxDiamondChannel[iFirstModuleWithDiamond]][0] );
00838 
00839          if( -1 < iFirstModuleWithReference)
00840             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference] &&
00841                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithReference]).iMultiplicity[fPar->iVftxReferenceChannel[iFirstModuleWithReference]] )
00842                for(Int_t iModule=1; iModule<MAX_FPGA_TDC; iModule++)
00843                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] && fPar->iVftxReferenceChannel[iModule] )
00844                   {
00845                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReferenceChannel[iModule]] )
00846                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReferenceChannel[iModule]][0] &&
00847                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithReference]).dTimeCorr[fPar->iVftxReferenceChannel[iFirstModuleWithReference]][0] )
00848                      fTdcResolutionRefCheck[iModule-1]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReferenceChannel[iModule]][0] -
00849                                 (fOutputEvent->fVftxBoards[iFirstModuleWithReference]).dTimeCorr[fPar->iVftxReferenceChannel[iFirstModuleWithReference]][0] );
00850 
00851                      if( 1 == fPar->uAutomaticOffsetEnable )
00852                         if( 5000 < fTdcResolutionRefCheck[iModule-1]->GetEntries() )
00853                         {
00854                            if( fTdcResolutionRefCheck[iModule-1]->GetMean() < - 2500 )
00855                               fPar->iAutomaticTdcOffset[iModule] = 1;
00856                            else if( 2500 < fTdcResolutionRefCheck[iModule-1]->GetMean() )
00857                               fPar->iAutomaticTdcOffset[iModule] = -1;
00858                         }
00859                   } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && fPar->iVftxReferenceChannel[iModule] )
00860 
00861          fOutputEvent->SetValid(kTRUE);
00862       } // if( 1 == fPar->uEnableCalib )
00863          else
00864          {
00865             if( 1 == fPar->uTimeHistEnable )
00866                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
00867                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
00868                      for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++) 
00869                         for( Int_t iMul = 0; iMul< TVftxBoardData::MaxMult; iMul++) 
00870                         { 
00871                            if( -1 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul] )
00872                               fTime[iModule][iChan]->Fill(
00873                                     (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul]
00874                                             - iTriggerTime[iModule]  );
00875                         }
00876          }// else of if( 1 == fPar->uEnableCalib )
00877       fOutputEvent->SetValid(kTRUE);
00878    } //  IsValid
00879    return;
00880 }