00001 #ifndef TVFTXPROC_H 00002 #define TVFTXPROC_H 00003 00004 #include "TGsiAug12Analysis.h" 00005 #include "TCBMBeamtimeProc.h" 00006 #include "MBSUNPACK/TMbsCrateEvent.h" 00007 #include "TTriglogEvent.h" 00008 #include "TVftxEvent.h" 00009 #include "TVftxParam.h" 00010 #include "../../mbs/cbmvme.h" 00011 00012 00013 #include "TGo4Picture.h" 00014 #include "TH1.h" 00015 #include "TH2.h" 00016 00017 #include "TFile.h" 00018 #include "TTree.h" 00019 #include <fstream> 00020 #include <vector> 00021 00022 #define SYNCH_CHANNEl 0 00023 00024 class TGo4EventElement; 00025 class TGo4MbsSubEvent; 00026 00027 class TVftxProc : public TCBMBeamtimeProc { 00028 // friend class TCBMBeamtimeProc; 00029 public: 00030 TVftxProc(const char* name = 0); 00031 virtual ~TVftxProc(); 00032 virtual void InitEvent(TGo4EventElement*); 00033 virtual void FinalizeEvent(); 00034 private: 00035 00036 // for each FPGA TDC we have header information 00037 // for each FPGA TDC channel we have coarse time, fine time, and future bit 00038 // it is multi-hit tdc so we need additional index 00039 UInt_t event_nr; 00040 Int_t headTime[MAX_FPGA_TDC]; 00041 00042 Int_t iFirstTime[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00043 Int_t iFirstCoarse[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00044 Int_t iFirstFine[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00045 Int_t iLastTime[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00046 Int_t iLastToT[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00047 Int_t iTriggerTime[MAX_FPGA_TDC]; 00048 00049 Int_t iNbHitsForCalib[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00050 Double_t dCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TDC_FIFO_FINE_CT+1]; 00051 Double_t dFirstTimecorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00052 Double_t dFirstFineTimecorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00053 Double_t dTimeCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TVftxBoardData::MaxMult]; 00054 Double_t dFineTimeCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TVftxBoardData::MaxMult]; 00055 00056 UInt_t uTotalMultiplicity[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00057 00058 TFile* fileCalibrationIn; 00059 TDirectory* oldDir; 00060 TH1 *fInitialCalibHisto[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00061 00062 TH1 *bitcontrol[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00063 TH1 *bitcontrolCoarse[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00064 TH1 *fEventSizeHeader1[MAX_FPGA_TDC]; 00065 TH1 *fEventSizeHeader2[MAX_FPGA_TDC]; 00066 TH1 *fTriggerType[MAX_FPGA_TDC]; 00067 TH1 *fTriggerTime[MAX_FPGA_TDC]; 00068 00069 TH1 *fChanUsage[MAX_FPGA_TDC]; 00070 TH1 *fChanEvents[MAX_FPGA_TDC]; 00071 TH1 *fChanDouble[MAX_FPGA_TDC]; 00072 TH1 *fChanFuture[MAX_FPGA_TDC]; 00073 TH2 *fChanMultip[MAX_FPGA_TDC]; 00074 00075 TH1 *fTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00076 TH1 *fToT[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00077 00078 TH1 *fFineTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00079 TH1 *fDnlCorr[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00080 TH1 *fCoarseTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00081 00082 TH2 *fFineTimeEvo[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00083 TH2 *fBinSizeEvo[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00084 UInt_t uInitialMbsTime; 00085 UInt_t uInitialVulomSync; 00086 00087 TH2 *fTdcChanStripMapping[ MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 ]; 00088 Int_t iMapIndex; 00089 00090 TH1 *fTdcResolutionDiamCheck[MAX_FPGA_TDC - 1]; 00091 Int_t iFirstModuleWithDiamond; 00092 TH2 *fDiamondTimeTriggerDep[MAX_FPGA_TDC]; 00093 00094 00095 TH1 *fTdcResolutionRefCheck[MAX_FPGA_TDC - 1]; 00096 Int_t iFirstModuleWithReference; 00097 protected: 00098 00099 TVftxParam * fPar; 00100 TMbsCrateEvent * fCrateInputEvent; 00101 TVftxEvent * fOutputEvent; 00102 TTriglogEvent* fTriglogInputEvent; 00103 00104 protected: 00105 00106 ClassDef(TVftxProc,1) 00107 }; 00108 00109 #endif //TVFTXPROC_H 00110
1.7.1