ROCsoft: beamtime/gsi-aug12/hd/go4/VFTX/TVftxProc.cxx (r4864/r3220) Source File

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00001 #include "TVftxProc.h"
00002 #include "TMbsCrateProc.h"
00003 
00004 #include "TTimeStamp.h"
00005 
00006 void TVftxProc::clear_tree_var()
00007 {
00008   for(Int_t i=0; i<MAX_FPGA_TDC; i++) 
00009   {
00010     headTime[i]=-1;
00011     for(Int_t j=0; j<FPGA_TDC_NBCHAN; j++) 
00012     {
00013       mult[i][j]=0;
00014       for (Int_t k=0; k<TVftxBoardData::MaxMult; k++) 
00015       {
00016          fineTime[i][j][k]=-1;
00017          coarseTime[i][j][k]=-1;
00018          futureBit[i][j][k]=0;
00019       } // for (Int_t k=0; k<TVftxBoardData::MaxMult; k++) 
00020     } // for(Int_t j=0; j<FPGA_TDC_NBCHAN; j++) 
00021   } // for(Int_t i=0; i<MAX_FPGA_TDC; i++) 
00022 }
00023 
00024 void TVftxProc::add_hit(Int_t mod, Int_t ichan, UInt_t iFineCounter, UInt_t iCoarseCounter, UInt_t bFutureBit)
00025 {
00026   if ((mod >= 0) && (mod < MAX_FPGA_TDC) && (ichan >= 0) && (ichan < FPGA_TDC_NBCHAN) ) {
00027     if( (mult[mod][ichan] < TVftxBoardData::MaxMult ) )
00028     {
00029       fineTime[mod][ichan][mult[mod][ichan]]=iFineCounter;
00030       coarseTime[mod][ichan][mult[mod][ichan]]=iCoarseCounter;
00031       futureBit[mod][ichan][mult[mod][ichan]]=bFutureBit;
00032       mult[mod][ichan]++;
00033     }
00034   } else {
00035     cout << "wrong module in add_hit: " << mod <<"/"<<MAX_FPGA_TDC<<" "<< ichan << "/"<<FPGA_TDC_NBCHAN<< endl;
00036   }
00037 }
00038 
00039 void TVftxProc::print_hit(Int_t mod, Int_t ichan, UInt_t iFineCounter, UInt_t iCoarseCounter, UInt_t bFutureBit)
00040 {
00041    if ((mod >= 0) && (mod < MAX_FPGA_TDC) && (ichan >= 0) && (ichan < FPGA_TDC_NBCHAN) && (mult[mod][ichan] < TVftxBoardData::MaxMult)) {
00042       cout << "mod:" << mod <<  " chan:" << ichan;
00043       cout << " ft:" << iFineCounter << " ct:" << iCoarseCounter << " fb:" << bFutureBit;
00044       cout << " mult:" << mult[mod][ichan] << endl;
00045    } else {
00046       cout << "wrong module in print_hit: " << mod << " " << ichan <<" "<<mult[mod][ichan]<< endl;
00047    }
00048 }
00049 TVftxProc::TVftxProc(const char* name) : TCBMBeamtimeProc(name),fCrateInputEvent(0), fOutputEvent(0),fTriglogInputEvent(0)
00050 {
00051    TGo4Log::Info("**** TVftxProc: Create instance %s" , name );
00052 
00053    fPar = (TVftxParam*) MakeParameter("VftxPar", "TVftxParam");
00054 
00055    //~ cout<<name<<endl;
00056    for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00057    { 
00058       //~ cout<<imodule<<" "<<name<<endl;
00059       if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00060       {
00061          fEventSizeHeader1[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader1_%d",imodule,imodule),
00062                      "Size of the event in event header", 256, -0.5, 255.5,"Size [words]");
00063          fEventSizeHeader2[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader2_%d",imodule,imodule),
00064                      "Size of the event in tdc header", 256, -0.5, 255.5,"Size [words]");
00065          fTriggerType[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerType%d",imodule,imodule),
00066                      "Trigger type in tdc header", 4, -0.5, 3.5,"Type []");
00067          fTriggerTime[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerTime%d",imodule,imodule),
00068                      "Time of the trigger in the coarse counter", 16383, 0, 16383,"Bin []");
00069                
00070          fChanUsage[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanUsage%d",imodule,imodule),
00071                    "Data on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00072          fChanEvents[imodule] = MakeTH1('I', Form("FPGA/ChanEvents%d",imodule),
00073                     "Data on channel during this event?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Events []");
00074                
00075          fChanFuture[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanFuture%d",imodule,imodule),
00076                     "Channel in future?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00077            
00078          fChanDouble[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanDouble%d",imodule,imodule),
00079                     "Double on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00080            
00081          fChanMultip[imodule] = MakeTH2('I', Form("FPGA/tdc%d/fChanMultip%d",imodule,imodule),
00082                     "Multiplicity per channel", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5, 32, 0, 32, "Channel []","Multiplicity []","Counts []");
00083       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00084       //~ cout<<"a "<<name<<endl;
00085       for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00086       {
00087       //~ cout<<"b "<<name<<" ";
00088          if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistEnable )
00089             fTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/time/chan%2dTime%d",imodule,ichan,imodule),
00090                    Form("Time to trigger Tdc %d channel %2d",imodule, ichan),
00091                    8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00092                
00093       //~ cout<<name<<" ";
00094          if( 1 == fPar->uFineHistEnable )
00095          {
00096             TString sHistoName = Form("chan%2dFineTime%d",ichan,imodule);
00097             TString sHistoFullPath = Form("FPGA/tdc%d/ft/%s",imodule, sHistoName.Data() );
00098             TString sHistoTitle = Form("FineTime Tdc %d channel %2d",imodule, ichan);
00099             fFineTime[imodule][ichan] = MakeTH1('I', sHistoFullPath,
00100                   sHistoTitle,
00101                   TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00102                   "Fine Time [bin]"); 
00103             TGo4Analysis::Instance()->ProtectObjects( sHistoName, "+C");
00104          }
00105       //~ cout<<name<<endl;
00106                               
00107          iNbHitsForCalib[imodule][ichan] = 0;
00108       }    
00109       //~ cout<<"b "<<name<<endl;
00110       if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable )
00111          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00112          {
00113             fFineTimeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%2dFineTimeEvo%d",imodule,ichan,imodule),
00114                   Form("FineTime Tdc %d channel %2d",imodule, ichan),
00115                   72, -0.5, 72 - 0.5,
00116                   TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00117                   "Time [h]", "Fine Time [bin]"); 
00118             fBinSizeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%2dBinSizeEvo%d",imodule,ichan,imodule),
00119                   Form("Bin Size Tdc %d channel %2d",imodule, ichan),
00120                   200, -0.5, 1000- 0.5,
00121                   50, -0.5, 50 - 0.5,
00122                   "Time [min]", "Bin Size [ps]"); 
00123          }
00124       uInitialMbsTime   = 0;
00125       uInitialVulomSync = 0;
00126       //~ cout<<"c "<<name<<endl;
00127       
00128       //histograms for the non-linear correction
00129       if( 1 == fPar->uEnableCalib )
00130       { 
00131          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00132          {    
00133             fDnlCorr[imodule][ichan] = MakeTH1('D', Form("FPGA/tdc%d/Dnl/chan%2dDnlCorr%d",imodule,ichan,imodule),
00134                       Form("DnlSum Tdc %d channel %2d",imodule, ichan),
00135                       TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00136                       "Fine Time [bin]");
00137          } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00138          
00139          if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTotHistoEnable )
00140             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN/2; ichan++)     
00141                fToT[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/tot/chan%2dToT%d",imodule,ichan,imodule),
00142                  Form("ToT Tdc %d channel %2d",imodule, ichan),
00143                  30000, -150000, 150000, "ToT [ps]");
00144       } // if( 1 == fPar->uEnableCalib )
00145       
00146       //~ cout<<"d "<<name<<endl;
00147       if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl)
00148       {
00149          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00150          {
00151             bitcontrol[imodule][ichan] = MakeTH1('I', 
00152                       Form("FPGA/tdc%d/bits%d/chan%2dBitcontrol%d",imodule,imodule,ichan,imodule),
00153                       Form("use of bits Tdc %d channel %2d",imodule, ichan),
00154                       TDC_FIFO_COARSE_CT_SHIFT, 0, TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00155             bitcontrolCoarse[imodule][ichan] = MakeTH1('I', 
00156                       Form("FPGA/tdc%d/bits%dCoarse/chan%2dBitcontrol%dCoarse",imodule,imodule,ichan,imodule),
00157                       Form("use of bits Tdc %d channel %2d",imodule, ichan),
00158                       TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT, 
00159                       0, TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00160          } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00161       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl)
00162       
00163       //~ cout<<"e "<<name<<endl;
00164       if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00165       {
00166          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00167          {
00168             fCoarseTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/ct/chan%2dCoarseTime%d",imodule,ichan,imodule),
00169                                                   Form("CoarseTime Tdc %d channel %2d",imodule, ichan),
00170                                                   TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT, -0.5, (TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT)-0.5,
00171                                                   "Coarse Time [bin]");
00172          } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00173       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00174       //~ cout<<"f "<<name<<endl;
00175    } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00176 
00177    if( 1 == fPar->uVftxCoincidenceMap )
00178    {
00179       /*
00180       fChannelStripMapping = MakeTH2('I', "FPGA/Mapping", "Channel during same event?",
00181                              MAX_FPGA_TDC*FPGA_TDC_NBCHAN, -0.5, MAX_FPGA_TDC*FPGA_TDC_NBCHAN - 0.5,
00182                              MAX_FPGA_TDC*FPGA_TDC_NBCHAN, -0.5, MAX_FPGA_TDC*FPGA_TDC_NBCHAN - 0.5,
00183                              "Channel 1 []","Channel 2 []","Events []");
00184       */
00185       iMapIndex = 0;
00186       for( Int_t iModule1 = 0; iModule1 < MAX_FPGA_TDC; iModule1 ++)
00187          for( Int_t iModule2 = iModule1; iModule2 < MAX_FPGA_TDC; iModule2 ++)
00188          {
00189             if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00190             {
00191                TGo4Log::Info("****Vftx monitor: Error creating mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00192                      iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule1, iModule2);
00193                break;
00194             }
00195             fTdcChanStripMapping[ iMapIndex ] =
00196                      MakeTH2('I', Form("FPGA/Mapp%d_%dVftx", iModule1, iModule2 ),
00197                                   Form("Channel during same event?, Tdc %d VS Tdc %d", iModule1, iModule2),
00198                                    FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00199                                    FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00200                                    Form("Channel Tdc #%d []", iModule1),
00201                                    Form("Channel Tdc #%d []", iModule2),"Events []");
00202             iMapIndex++;
00203          }
00204    } // if( 1 == fPar->uVftxCoincidenceMap )
00205    
00206    //define root tree
00207    // initialize variables
00208    vTimecorr = new std::vector<Double_t>;
00209    vFineTimecorr = new std::vector<Double_t>;
00210    vTimecorr->resize( FPGA_TDC_NBCHAN );
00211    vFineTimecorr->resize( FPGA_TDC_NBCHAN );
00212  
00213    if( 1 == fPar->iRootOutput || 1 == fPar->iRootDisplay )
00214    {
00215       TGo4Log::Info("****Vftx monitor: Create tree ");
00216       if( 1 == fPar->iRootOutput )
00217       {
00218          cout<<gDirectory->GetPath()<<endl;
00219          oldDir = gDirectory;
00220             
00221          sOutputFilename = fPar->sOutputFilename;
00222          fRootOut= new TFile(sOutputFilename, "RECREATE", "TTree file from LMD for FPGA TDC", 9);
00223          sOutputFilename += ":/";
00224          gDirectory->Cd(sOutputFilename);
00225       }
00226       
00227       rawTree = new TTree("fpgaTree", "FPGA TDC TREE");
00228       TGo4Log::Info("Tree created in %s", gDirectory->GetPath() );
00229       
00230       // To prevent having multiple trees when opening the file with Go4
00231       rawTree->SetAutoFlush(0);
00232       
00233       rawTree->Branch("event_nr",&event_nr,"event_nr/i");
00234       rawTree->Branch("trigTime",headTime,    Form("[%d]/I", MAX_FPGA_TDC) );
00235       rawTree->Branch("mult",mult,            Form("mult[%d][%d]/I", MAX_FPGA_TDC, FPGA_TDC_NBCHAN) );
00236       rawTree->Branch("fineTime",fineTime,    Form("fineTime[%d][%d][%d]/I", 
00237                                                    MAX_FPGA_TDC, FPGA_TDC_NBCHAN, TVftxBoardData::MaxMult) );
00238       rawTree->Branch("coarseTime",coarseTime,Form("coarseTime[%d][%d][%d]/I", 
00239                                                    MAX_FPGA_TDC, FPGA_TDC_NBCHAN, TVftxBoardData::MaxMult) );
00240       rawTree->Branch("futureBit",futureBit,  Form("futureBit[%d][%d][%d]/i", 
00241                                                    MAX_FPGA_TDC, FPGA_TDC_NBCHAN, TVftxBoardData::MaxMult) );
00242       rawTree->Branch( "vTimecorr", "std::vector< Double_t >", &(vTimecorr) );
00243       rawTree->Branch( "vFineTimecorr", "std::vector< Double_t >", &(vFineTimecorr) );
00244 
00245 
00246       rawTree->SetDirectory(gDirectory);
00247       
00248       if( 1 == fPar->iRootOutput )
00249       {
00250          gDirectory->Cd(oldDir->GetPath());
00251          cout<<gDirectory->GetPath()<<endl;
00252       }
00253       if( 1 == fPar->iRootDisplay )
00254          TGsiAug12Analysis::Instance()->AddTree(rawTree);
00255       
00256       TGo4Log::Info("Vftx monitor: Created tree");
00257       event_nr = 0;
00258    } // if( 1 == fPar->iRootOutput || 1 == fPar->iRootDisplay )
00259    
00260    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00261         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00262         1 == fPar->uEnableCalib )
00263    {
00264       TString sInitalCalibHistoName = "";
00265       fileCalibrationIn = new TFile( fPar->sInitialCalibrationFilename, "READ");
00266       
00267       if( kTRUE == fileCalibrationIn->IsOpen() )
00268       {
00269          TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00270          TGo4Log::Info("%s", sInfoLoading.Data() );
00271          sInfoLoading = "         ";
00272          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00273             sInfoLoading += Form("%2d ", ichan);
00274          TGo4Log::Info("%s", sInfoLoading.Data() );
00275 
00276          //define correction variables
00277          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00278          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00279 
00280          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00281          {
00282             sInfoLoading = Form("tdc #%2d: ",imodule );
00283             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00284             {
00285                fInitialCalibHisto[imodule][ichan] = 0;
00286                sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00287                fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHisto[imodule][ichan]);
00288                
00289                if( 0 == fInitialCalibHisto[imodule][ichan] )
00290                   sInfoLoading += " 0 ";
00291                   else sInfoLoading += " 1 ";
00292 
00293                if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00294                {
00295                   // Try to use initial calibration histo always
00296                   fDnlCorr[imodule][ichan]->Reset();
00297                   //set a the sum to zero before summing over all bins in one channel
00298                   iSum[imodule][ichan] = 0;
00299                   Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00300 
00301                   for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00302                   {
00303                      Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00304                                          (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00305                      //Looking for the used bins
00306                      if( iBinContent <= 0)
00307                      {
00308                         bincontrol[ibin] = kFALSE;
00309                      }
00310                      else if( iBinContent > 0)
00311                      {
00312                         bincontrol[ibin] = kTRUE;
00313                      }
00314 
00315                      // build the sum of all bin content
00316                      if(bincontrol[ibin])
00317                      {
00318              iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00319              dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00320              if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable &&
00321                  2 == iNbHitsForCalib[imodule][ichan]%10000 )
00322                fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0,
00323                            CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00324                      }else
00325                      {
00326                         if( 0 < ibin)
00327                            dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00328                            else dCorr[imodule][ichan][ibin]=0;
00329                      }
00330                      fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00331                   } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00332                } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00333             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00334             TGo4Log::Info("%s", sInfoLoading.Data() );
00335          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00336       } // if( kTRUE == fileCalibrationIn->IsOpen() )
00337          else
00338          { 
00339             TGo4Log::Info("Could not open %s to load initial VFTX calibration, please check setting in Vftx_options.txt", 
00340                             fPar->sInitialCalibrationFilename.Data() );
00341             for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00342                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00343                   fInitialCalibHisto[imodule][ichan] = 0;
00344          } // else of if( kTRUE == fileCalibrationIn->IsOpen() )
00345 //      fileCalibrationIn->Close();
00346    } // if(  sInitialCalibrationFilename OK and 1 == fPar->uEnableCalib)
00347 
00348    //~ TGo4Log::Info("**** TVftxProc: Instance %s created", name );
00349 }
00350 
00351 
00352 TVftxProc::~TVftxProc()
00353 {
00354    cout << "**** TVftxProc: Delete instance " << endl;
00355    if( 1 == fPar->iRootOutput)
00356    {
00357       gDirectory->Cd(sOutputFilename);
00358 
00359       rawTree->SetDirectory(gDirectory);
00360 
00361       fRootOut->Write("");
00362 
00363       fRootOut->Close();
00364 
00365       gDirectory->Cd(oldDir->GetPath());
00366    } // if( 1 == fPar->iRootOutput)   
00367    
00368    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00369         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00370         1 == fPar->uEnableCalib &&
00371         kTRUE == fileCalibrationIn->IsOpen() )
00372       fileCalibrationIn->Close();
00373       
00374    if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00375    {
00376       TTimeStamp timeCurrent;
00377       oldDir = gDirectory;
00378       TString sCalibOutFilename = Form("./VftxCalibHistos_%u_%u.root", timeCurrent.GetDate( kFALSE), timeCurrent.GetTime( kFALSE) );
00379       TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE", 
00380                                             Form("Calibration Data for VFTX, saved from analysis on %s", timeCurrent.AsString("lc") ), 
00381                                             9);
00382       if( kTRUE == fileCalibrationOut->IsOpen() )
00383       {
00384          sCalibOutFilename += ":/";
00385          gDirectory->Cd(sCalibOutFilename);
00386          TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00387          TGo4Log::Info("%s", sInfoSaving.Data() );
00388          sInfoSaving = "         ";
00389          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00390             sInfoSaving += Form("%2d ", ichan);
00391          TGo4Log::Info("%s", sInfoSaving.Data() );
00392          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00393          {
00394             sInfoSaving = Form("tdc #%2d: ",imodule );
00395             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00396             {
00397                if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00398                {
00399                fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00400                                                  TObject::kOverwrite);
00401                sInfoSaving += " 1 ";
00402                }
00403                   else sInfoSaving += " 0 ";
00404             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00405             TGo4Log::Info("%s", sInfoSaving.Data() );
00406          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00407          //fileCalibrationOut->Write("",TObject::kOverwrite);
00408          fileCalibrationOut->Close();
00409          TGo4Log::Info("Calibration data saved in %s", sCalibOutFilename.Data() );
00410       } // if( kTRUE == fileCalibrationOut->IsOpen() )
00411          else TGo4Log::Warn("Error when deleting TVftxProc: Unable to open root file %s to save calibration data, please check settings",
00412                               sCalibOutFilename.Data() );
00413       gDirectory->Cd(oldDir->GetPath());
00414    } // if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00415 }
00416 
00417 void TVftxProc::InitEvent(TGo4EventElement* outevnt)
00418 {
00419    // first assign input event:
00420    // since input event object is never discarded within processor lifetime,
00421    // we just search for subevent by name once to speed up processing
00422 
00423    //cout << "VftxProc Init Event " <<  endl;
00424 
00425    if(fCrateInputEvent==0)
00426    {
00427       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(GetInputEvent());
00428       if(btevent)
00429       {
00430          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(btevent->GetSubEvent("MBSCRATE"));
00431          fTriglogInputEvent=dynamic_cast<TTriglogEvent*>(btevent->GetSubEvent("TRIGLOG"));
00432       }
00433       else
00434       {
00435          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(GetInputEvent());
00436       }
00437       if(fCrateInputEvent==0) {
00438         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event is not a TMbsCrateEvent!!! STOP GO4");
00439       }
00440       if(fTriglogInputEvent==0) {
00441         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event has no TTriglogEvent!!! STOP GO4");
00442       }
00443    }
00444    // then assign output event
00445 
00446    // since output event object is never discarded within processor lifetime,
00447    // we just search for subevent by name once to speed up processing
00448    if(fOutputEvent==0)
00449    {
00450       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(outevnt);
00451       if(btevent)
00452       {
00453          fOutputEvent=dynamic_cast<TVftxEvent*>(btevent->GetSubEvent("VFTX"));
00454       }
00455       else
00456       {
00457 
00458          fOutputEvent= dynamic_cast<TVftxEvent*>(outevnt);
00459       }
00460       if(fOutputEvent==0) {
00461         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: output event is not a TVftxEvent!!! STOP GO4");
00462       }
00463       else {
00464          //     BuildEvent(dynamic_cast<TGo4MbsSubEvent*>(btevent->GetSubEvent("MBSCRATE")));
00465       }
00466    }
00467 }
00468 
00469 void TVftxProc::FinalizeEvent()
00470 {
00471   //   cout << "**** TVftxProc: Finalize Event " << endl;
00472   BuildMyEvent();
00473   //if (fCrateInputEvent->IsValid()) {
00474       // for (int n=0;n<MAX_FPGA_TDC;n++) {
00475       //   unsigned num_hits = fCrateInputEvent->fFPGA[n].size();
00476       //   cout << "FPGA " << n << " has " << num_hits << " hits"<< endl;
00477       // }
00478 }
00479 
00480 //-----------------------------------------------------------
00481 // event function
00482 //void TVftxProc::BuildEvent(TGo4MbsSubEvent* subevt)
00483 void TVftxProc::BuildMyEvent()
00484 {
00485    if (fCrateInputEvent->IsValid()) 
00486    {
00487       // variables
00488       Int_t imodule = 0;
00489       Int_t iEvtSizeHeader1[MAX_FPGA_TDC];
00490       Int_t iEvtSizeHeader2[MAX_FPGA_TDC];
00491       for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++) 
00492       {
00493          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00494          {
00495             iFirstTime[imodule][ichan]     = -1;
00496             iFirstCoarse[imodule][ichan]   = -1;
00497             iFirstFine[imodule][ichan]     = -1;
00498             dFirstTimecorr[imodule][ichan] = -1;
00499             dFirstFineTimecorr[imodule][ichan] = -1;
00500             iLastTime[imodule][ichan]    = 0;
00501             for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00502             {
00503                dTimeCorr[imodule][ichan][imul] = -1;
00504                dFineTimeCorr[imodule][ichan][imul] = -1;
00505             }
00506             uTotalMultiplicity[imodule][ichan]    = 0;
00507          }
00508          iTriggerTime[imodule] = 0;
00509       }
00510       clear_tree_var();
00511       imodule = 0;
00512       // fill histograms    
00513       for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++) {
00514          unsigned num_hits = fCrateInputEvent->fFPGA[fpga].size(); // per tdc
00515          imodule  = fpga;
00516          
00517          if( 0 == num_hits && 0 == fCrateInputEvent->fFPGAHEAD[fpga].size() ) // check if fpga data are there
00518             continue;
00519          iEvtSizeHeader1[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).nr_data;
00520          iEvtSizeHeader2[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_nd;
00521          iTriggerTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00522          headTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00523          
00524          if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00525          {
00526             fEventSizeHeader1[imodule]->Fill( iEvtSizeHeader1[imodule] );
00527             fEventSizeHeader2[imodule]->Fill( iEvtSizeHeader2[imodule] );
00528             fTriggerType[imodule]->Fill(fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_tt);
00529             fTriggerTime[imodule]->Fill( iTriggerTime[imodule] );
00530          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00531          
00532          (fOutputEvent->fVftxBoards[imodule]).iTriggerTime = headTime[imodule];
00533          
00534          // cout<<" FPGA "<<fpga<<" Processing hit nb: "<<num_hits<<endl;
00535          for(unsigned i = 0; i<num_hits; i++) 
00536          {
00537             uint32_t ichan =  fCrateInputEvent->fFPGA[fpga].at(i).ch_ix;
00538             uint32_t bFutureBit = fCrateInputEvent->fFPGA[fpga].at(i).future_bit;
00539             int32_t iCoarseCounter =  fCrateInputEvent->fFPGA[fpga].at(i).coarse_ct;
00540             int32_t iFineCounter =  fCrateInputEvent->fFPGA[fpga].at(i).ch_tim;
00541             // cout<<"hit: "<<i<<" chan: "<<ichan<<" future: "<<bFutureBit<<" ct:"<<iCoarseCounter<<" ft:"<<iFineCounter<<endl;
00542             // for given module add data
00543             Int_t channel=ichan; 
00544             add_hit(imodule,channel,iFineCounter,iCoarseCounter,bFutureBit);
00545                
00546             if( (imodule >= 0) && (imodule < MAX_FPGA_TDC) && 
00547                 (channel >= 0) && (channel < FPGA_TDC_NBCHAN) )
00548             {
00549 
00550                if( ((fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] < TVftxBoardData::TVftxBoardData::MaxMult) )
00551                {
00552                   (fOutputEvent->fVftxBoards[imodule]).iFineTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]   = iFineCounter;
00553                   (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ] = iCoarseCounter;
00554                   (fOutputEvent->fVftxBoards[imodule]).uFutureBit[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]  = bFutureBit;
00555                   (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel]++;
00556                }
00557                uTotalMultiplicity[imodule][channel]++;
00558             }
00559                else continue;
00560         
00561             //Calculation of non-linear Correction
00562             if( 0 == uInitialMbsTime )
00563             {
00564                uInitialMbsTime   = fTriglogInputEvent->fMbsTimeSecs;
00565                uInitialVulomSync = fTriglogInputEvent->fVulomSyncNumber;
00566             }
00567             if( 1 == fPar->uFineHistEnable )
00568             {
00569                if( 0 == fFineTime[imodule][ichan]->GetEntries() )
00570                   iNbHitsForCalib[imodule][ichan] = 0;
00571                   
00572                fFineTime[imodule][ichan]->Fill(iFineCounter);
00573                
00574                iNbHitsForCalib[imodule][ichan] ++;
00575                if( fPar->iMinNbHitsCalib == iNbHitsForCalib[imodule][ichan] )
00576                   TGo4Log::Info("FPGA TDC: Calibration data ok for module %d channel %d, after %d events", imodule, ichan, fTriglogInputEvent->fVulomSyncNumber - uInitialVulomSync);
00577             }
00578             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable )
00579                fFineTimeEvo[imodule][ichan]->Fill( UInt_t((fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/3600), iFineCounter);
00580           
00581             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00582                fCoarseTime[imodule][ichan]->Fill(iCoarseCounter);
00583           
00584             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00585             {
00586                for (uint16_t ibit = 0; ibit <= 9; ibit++) 
00587                   if ((iFineCounter >> ibit) & 0x1) bitcontrol[imodule][ichan]->Fill( ibit );
00588                for (uint16_t ibit = 0; ibit <= 15; ibit++) 
00589                   if ((iCoarseCounter >> ibit) & 0x1) bitcontrolCoarse[imodule][ichan]->Fill( ibit );
00590             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00591 
00592             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00593             {
00594                fChanUsage[imodule]->Fill(ichan);
00595                if (bFutureBit) fChanFuture[imodule]->Fill(ichan);
00596             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00597           
00598             if (iLastTime[imodule][ichan])
00599             {
00600                if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00601                   fChanDouble[imodule]->Fill(ichan);
00602             }
00603             else
00604             {
00605                iFirstCoarse[imodule][ichan] = iCoarseCounter;
00606                iFirstFine[imodule][ichan]   = iFineCounter;
00607                iFirstTime[imodule][ichan]   = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)
00608                                                + iFineCounter; // Modif PAL to re-add the coarse counter shift
00609             }
00610 
00611             iLastTime[imodule][ichan] = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)  + iFineCounter;
00612          } // for(unsigned i = 0; i<num_hits; i++)
00613             
00614          // cout<<" FPGA "<<fpga<<" Processed hit nb: "<<num_hits<<endl;
00615       } // for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++)
00616       
00617       if( 1 == fPar->uEnableCalib )
00618       {
00619          //define correction variables
00620          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00621          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00622         
00623          for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00624          {
00625             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00626             {
00627                // cout<<" Test Corr Tdc "<<imodule<<" chan "<<ichan<<endl;
00628                if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]  &&
00629                    -1 <  fPar->iMinNbHitsCalib)
00630                {
00631                   if(// iNbHitsForCalib[imodule][ichan]< (2*fPar->iMinNbHitsCalib) ||
00632                     0 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00633                   {
00634                      fDnlCorr[imodule][ichan]->Reset();
00635                      //set a the sum to zero before summing over all bins in one channel
00636                      iSum[imodule][ichan] = 0;
00637                      Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() );
00638                      
00639                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00640                      {
00641                         Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1));
00642                         //Looking for the used bins
00643                         if( iBinContent <= 0)
00644                         {
00645                            bincontrol[ibin] = kFALSE;
00646                         }
00647                         else if( iBinContent > 0)
00648                         {
00649                            bincontrol[ibin] = kTRUE;
00650                         }
00651                            
00652                         // build the sum of all bin content
00653                         if(bincontrol[ibin])
00654                         {
00655                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00656                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00657                 if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00658                     0 == iNbHitsForCalib[imodule][ichan]%10000 )
00659                   fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00660                               CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00661                         }else
00662                         {
00663                            if( 0 < ibin)
00664                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00665                               else dCorr[imodule][ichan][ibin]=0;
00666                         }      
00667                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00668                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00669                   } // if( iNbHitsForCalib[imodule][ichan]<1e6 || 0 == iNbHitsForCalib[imodule][ichan]%40000 )
00670                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00671                   else if( -1 < fPar->iMinNbHitsCalib )
00672                   {
00673                      // Try to use initial calibration histo as long as under 
00674                      // the minimal number of hits in calibration
00675                      if( 0 != fInitialCalibHisto[imodule][ichan] &&
00676                          2 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00677                      {
00678                         fDnlCorr[imodule][ichan]->Reset();
00679                         //set a the sum to zero before summing over all bins in one channel
00680                         iSum[imodule][ichan] = 0;
00681                         Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() ) + 
00682                                                         (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00683                         
00684                         for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00685                         {
00686                            Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00687                                                (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00688                            //Looking for the used bins
00689                            if( iBinContent <= 0)
00690                            {
00691                               bincontrol[ibin] = kFALSE;
00692                            }
00693                            else if( iBinContent > 0)
00694                            {
00695                               bincontrol[ibin] = kTRUE;
00696                            }
00697                               
00698                            // build the sum of all bin content
00699                            if(bincontrol[ibin])
00700                            {
00701                    iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00702                    dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00703                    if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00704                        2 == iNbHitsForCalib[imodule][ichan]%10000 )
00705                      fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00706                                  CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00707                            }else
00708                            {
00709                               if( 0 < ibin)
00710                                  dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00711                                  else dCorr[imodule][ichan][ibin]=0;
00712                            }      
00713                            fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00714                         } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00715                      } //  if( 0 != fInitialCalibHisto[imodule][ichan] )
00716                   } // else of else if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00717                
00718                if( ( -1<fPar->iMinNbHitsCalib && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]) ||
00719                    0 != fInitialCalibHisto[imodule][ichan] )
00720                {
00721                   if( 0<=iFirstCoarse[imodule][ichan] || 0<=iFirstFine[imodule][ichan] )
00722                   {
00723                     dFirstTimecorr[imodule][ichan] = iFirstCoarse[imodule][ichan]*CLOCK_TIME 
00724                              +  (1 - dCorr[imodule][ichan][iFirstFine[imodule][ichan]])*CLOCK_TIME;  
00725                    dFirstFineTimecorr[imodule][ichan] = dCorr[imodule][ichan][iFirstFine[imodule][ichan]]*CLOCK_TIME;  
00726                   }  
00727                   for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00728                      if( 0<=(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul] || 
00729                          0<=(fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul])
00730                      {
00731                         dTimeCorr[imodule][ichan][imul] = (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul]*CLOCK_TIME
00732                             +  (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME; 
00733                         dFineTimeCorr[imodule][ichan][imul] = (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME;
00734                         
00735                         // Fill it in output event
00736                         (fOutputEvent->fVftxBoards[imodule]).dTimeCorr[ichan][imul]     = dTimeCorr[imodule][ichan][imul];
00737                         (fOutputEvent->fVftxBoards[imodule]).dFineTimeCorr[ichan][imul] = dFineTimeCorr[imodule][ichan][imul];
00738                      } // if( 0<=fineTime[imodule][ichan][imul] || 0<=coarseTime[imodule][ichan][imul])
00739                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])
00740                
00741                // cout<<"Corr Tdc "<<imodule<<" chan "<<ichan<<" ok"<<endl;
00742             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00743                
00744             //Compare corrected time with trigger time 
00745             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00746             {
00747 #if defined(VERSION_VFTX) || defined(VERSION_VFTX_28) // 1 TDC mode, chan = Time, chan +1 = Tot
00748                Double_t dTimeToTrigger[FPGA_TDC_NBCHAN];
00749                Double_t dToT[FPGA_TDC_NBCHAN];
00750                for( Int_t ichan = 0; ichan < FPGA_TDC_NBCHAN; ichan ++)
00751                {
00752                   if( 1 == fPar->uTimeHistEnable && 
00753                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])&&
00754                       0 < iFirstTime[imodule][ichan] )
00755                   {
00756                      dTimeToTrigger[ichan] = dFirstTimecorr[imodule][ichan] - iTriggerTime[imodule]*CLOCK_TIME;
00757                      if( 1000 < iFirstCoarse[imodule][ichan*2+1] - iTriggerTime[imodule])
00758                         dToT[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00759                      if( iFirstCoarse[imodule][ichan*2+1] - iTriggerTime[imodule] < -1000 )
00760                         dToT[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00761                      fTime[imodule][ichan]->Fill( dTimeToTrigger[ichan] );
00762                   }
00763                   if( 1 == fPar->uTotHistoEnable && ichan < FPGA_TDC_NBCHAN/2 )
00764                      if( 0 < iFirstTime[imodule][ichan*2] && 0 < iFirstTime[imodule][ichan*2+1] &&
00765                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2]   || 0 != fInitialCalibHisto[imodule][ichan*2]  )&&
00766                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2+1] || 0 != fInitialCalibHisto[imodule][ichan*2+1]) )
00767                      {
00768                         dToT[ichan] =  dFirstTimecorr[imodule][ichan*2] -  dFirstTimecorr[imodule][ichan*2+1] ;
00769                         if( 1000 < iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] )
00770                            dToT[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00771                         if( iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] < -1000 )
00772                            dToT[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00773                         fToT[imodule][ichan]->Fill(dToT[ichan]);
00774                      } // if( 1 == fPar->uTotHistoEnable && .... )
00775                }
00776 #else
00777                if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][0])
00778                   fTime[imodule][0]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME - dFirstTimecorr[imodule][0]);
00779                if( 1 == fPar->uTotHistoEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0]
00780                   && fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00781                   fToT[0]->Fill(((Double_t)iTriggerTime[0]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[0][0] 
00782                              - (((Double_t)iTriggerTime[1]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[1][0]));
00783                Double_t dToT[FPGA_TDC_NBCHAN];
00784                for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00785                {
00786                   if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00787                      fTime[imodule][ichan]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME
00788                                                   - dFirstTimecorr[imodule][ichan]);
00789                   if( 1 == fPar->uTotHistoEnable && 
00790                       0 < iFirstTime[0][ichan] && 0 < iFirstTime[1][ichan] &&
00791                       0 < iFirstTime[0][0]     && 0 < iFirstTime[1][0]  && 
00792                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00793                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][1] &&
00794                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00795                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00796                   {
00797                       dToT[ichan] = (iTriggerTime[0]*(Double_t)CLOCK_TIME )  - dFirstTimecorr[0][ichan] 
00798                         - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][ichan])
00799                         - ( (iTriggerTime[0]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[0][0] 
00800                        - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][0])) ;
00801                      fToT[ichan]->Fill(dToT[ichan]);
00802                   } // if( 1 == fPar->uTotHistoEnable && .... )
00803                } // for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00804 #endif
00805             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00806          } // for(  imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00807                   
00808          //fill the root tree
00809          if( 1 == fPar->iRootOutput || 1 == fPar->iRootDisplay )
00810          {
00811             //set parameters
00812             for(Int_t ichan=0; ichan<FPGA_TDC_NBCHAN; ichan++) 
00813             {
00814                (*vTimecorr)[ichan] = dFirstTimecorr[0][ichan];
00815                (*vFineTimecorr)[ichan] = dFirstFineTimecorr[0][ichan];
00816             } // for(Int_t ichan=0; ichan<16; ichan++)
00817             
00818             //Fill root tree
00819             rawTree->Fill();
00820             event_nr++;
00821          } // if( 1 == fPar->iRootOutput || 1 == fPar->iRootDisplay )
00822 
00823          // Fill the output event
00824          for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
00825          {
00826             for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++) 
00827             {
00828                // Go back to index for VFTX internal map
00829                if( 1 == fPar->uVftxCoincidenceMap )
00830                   iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
00831                            - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2;
00832 
00833                //~ for( Int_t iMul = 0; iMul< TVftxBoardData::TVftxBoardData::MaxMult; iMul++) 
00834                   //~ if( 0 <= dTimeCorr[iModule][iChan][iMul] )
00835                   //~ { 
00836    //~ (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iMul]     = dTimeCorr[iModule][iChan][iMul];
00837    //~ (fOutputEvent->fVftxBoards[iModule]).dFineTimeCorr[iChan][iMul] = dFineTimeCorr[iModule][iChan][iMul];
00838                   //~ }
00839                if( 1 == fPar->uVftxCalHistosEnabled[iModule]  &&
00840                    0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan] )
00841                {
00842                   fChanEvents[iModule]->Fill(iChan);
00843                   if( 1 == fPar->uVftxCoincidenceMap )
00844                   {
00845                      if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00846                      {
00847                         TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00848                               iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule);
00849                         return;
00850                      } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00851                      for(Int_t iChan2=iChan+1; iChan2<FPGA_TDC_NBCHAN; iChan2++)
00852                         if( 1 == fPar->uVftxCalHistosEnabled[iModule] && 0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan2] )
00853                         {
00854                            /*
00855                           fChannelStripMapping->Fill( iModule*FPGA_TDC_NBCHAN + iChan,
00856                                                        iModule*FPGA_TDC_NBCHAN + iChan2 );
00857                                                        */
00858                            fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
00859                         }
00860 
00861                      for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
00862                      {
00863                         // Find index for corresponding VFTX against VFTX map
00864                         iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
00865                                  - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2
00866                                  + (iModule2 - iModule);
00867                         if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00868                         {
00869                            TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00870                                  iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule2);
00871                            return;
00872                         } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00873                         for(Int_t iChan2=0; iChan2<FPGA_TDC_NBCHAN; iChan2++)
00874                            if( 1 == fPar->uVftxCalHistosEnabled[iModule2] && 0<(fOutputEvent->fVftxBoards[iModule2]).iMultiplicity[iChan2] )
00875                            {
00876                               /*
00877                               fChannelStripMapping->Fill( iModule*FPGA_TDC_NBCHAN  + iChan,
00878                                                           iModule2*FPGA_TDC_NBCHAN + iChan2 );
00879                                */
00880                               fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
00881                            }
00882                      } // for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
00883                   } // if( 1 == fPar->uVftxCoincidenceMap )
00884                } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && chan1 there)
00885 
00886                if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
00887                   fChanMultip[iModule]->Fill(iChan, uTotalMultiplicity[iModule][iChan] );
00888             } // for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++)
00889          } //  for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
00890          fOutputEvent->SetValid(kTRUE);
00891       } // if( 1 == fPar->uEnableCalib )
00892          else
00893          {
00894             if( 1 == fPar->uTimeHistEnable )
00895                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
00896                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
00897                      for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++) 
00898                         for( Int_t iMul = 0; iMul< TVftxBoardData::MaxMult; iMul++) 
00899                         { 
00900                            if( -1 < coarseTime[iModule][iChan][iMul] )
00901                               fTime[iModule][iChan]->Fill( coarseTime[iModule][iChan][iMul] - iTriggerTime[iModule]  );
00902                         }
00903          }// else of if( 1 == fPar->uEnableCalib )
00904   } //  IsValid
00905 
00906   return;
00907 }