ROCsoft: beamtime/gsi-aug12/prod/go4/VFTX/TVftxProc.cxx (r4864/r4011) Source File

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00001 #include "TVftxProc.h"
00002 #include "MBSUNPACK/TMbsCrateProc.h"
00003 
00004 #include "TTimeStamp.h"
00005 
00006 TVftxProc::TVftxProc(const char* name) : TCBMBeamtimeProc(name),fCrateInputEvent(0), fOutputEvent(0),fTriglogInputEvent(0)
00007 {
00008    TGo4Log::Info("**** TVftxProc: Create instance %s" , name );
00009 
00010    fPar = (TVftxParam*) MakeParameter("VftxPar", "TVftxParam");
00011 
00012    //~ cout<<name<<endl;
00013    iFirstModuleWithReference2   = -1;
00014    iFirstModuleWithReference1 = -1;
00015 
00016    // If the main reference tdc is defined, try to use its reference channels
00017    if( -1 < fPar->iMainReferenceTdc)
00018    {
00019       if( -1 < fPar->iVftxReference1Channel[fPar->iMainReferenceTdc])
00020          iFirstModuleWithReference1 = fPar->iMainReferenceTdc;
00021       if( -1 < fPar->iVftxReference2Channel[fPar->iMainReferenceTdc])
00022          iFirstModuleWithReference2 = fPar->iMainReferenceTdc;
00023    } // if( -1 < fPar->iMainReferenceTdc)
00024 
00025    for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00026    { 
00027       if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00028       {
00029          fEventSizeHeader1[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader1_%d",imodule,imodule),
00030                      "Size of the event in event header", 256, -0.5, 255.5,"Size [words]");
00031          fEventSizeHeader2[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader2_%d",imodule,imodule),
00032                      "Size of the event in tdc header", 256, -0.5, 255.5,"Size [words]");
00033          fTriggerType[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerType%d",imodule,imodule),
00034                      "Trigger type in tdc header", 4, -0.5, 3.5,"Type []");
00035          fTriggerTime[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerTime%d",imodule,imodule),
00036                      "Time of the trigger in the coarse counter", 16383, 0, 16383,"Bin []");
00037                
00038          fChanUsage[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanUsage%d",imodule,imodule),
00039                    "Data on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00040          fChanEvents[imodule] = MakeTH1('I', Form("FPGA/ChanEvents%d",imodule),
00041                     "Data on channel during this event?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Events []");
00042                
00043          fChanFuture[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanFuture%d",imodule,imodule),
00044                     "Channel in future?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00045            
00046          fChanDouble[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanDouble%d",imodule,imodule),
00047                     "Double on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00048            
00049          fChanMultip[imodule] = MakeTH2('I', Form("FPGA/tdc%d/fChanMultip%d",imodule,imodule),
00050                     "Multiplicity per channel", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00051                     TVftxBoardData::MaxMult+1, 0, TVftxBoardData::MaxMult+1, "Channel []","Multiplicity []","Counts []");
00052 
00053          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00054          {
00055             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistEnable )
00056                fTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/time/chan%02dTime%d",imodule,ichan,imodule),
00057                       Form("Time to trigger Tdc %d channel %2d",imodule, ichan),
00058                       8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00059 
00060             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistSinglesEnable )
00061                fTimeSingles[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/timeSingles/chan%02dTimeSingles%d",imodule,ichan,imodule),
00062                       Form("Time to trigger Tdc %d channel %2d for events with only one hit",imodule, ichan),
00063                       8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00064 
00065             if( 1 == fPar->uMultiHitsDistanceHistoEnable)
00066                fMultihitsDistance[imodule][ichan]
00067                      = MakeTH2('I', Form("FPGA/tdc%d/multiDist/chan%02dMultiDist%d",imodule,ichan,imodule),
00068                               Form("Time to previous hit for multiple hits Tdc %d channel %2d",imodule, ichan),
00069                               1000, 0, 100000,
00070                               TVftxBoardData::MaxMult, 1, TVftxBoardData::MaxMult + 1,
00071                               "T(n) - T(n-1) [ps]",
00072                               "n (Multiple hits index) []");
00073 
00074             if( 1 == fPar->uFineHistEnable )
00075             {
00076                TString sHistoName = Form("chan%02dFineTime%d",ichan,imodule);
00077                TString sHistoFullPath = Form("FPGA/tdc%d/ft/%s",imodule, sHistoName.Data() );
00078                TString sHistoTitle = Form("FineTime Tdc %d channel %2d",imodule, ichan);
00079                fFineTime[imodule][ichan] = MakeTH1('I', sHistoFullPath,
00080                      sHistoTitle,
00081                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00082                      "Fine Time [bin]");
00083                fFineTime[imodule][ichan]->Reset();
00084                TGo4Analysis::Instance()->ProtectObjects( sHistoName, "+C");
00085             }
00086 
00087             iNbHitsForCalib[imodule][ichan] = 0;
00088             for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00089                dCorr[imodule][ichan][ibin] = 0;
00090          }
00091          if( 1 == fPar->uFineEvolutionHistEnable )
00092             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00093             {
00094                fFineTimeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%02dFineTimeEvo%d",imodule,ichan,imodule),
00095                      Form("FineTime Tdc %d channel %2d",imodule, ichan),
00096                      72, -0.5, 72 - 0.5,
00097                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00098                      "Time [h]", "Fine Time [bin]");
00099                fBinSizeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%02dBinSizeEvo%d",imodule,ichan,imodule),
00100                      Form("Bin Size Tdc %d channel %2d",imodule, ichan),
00101                      200, -0.5, 1000- 0.5,
00102                      50, -0.5, 50 - 0.5,
00103                      "Time [min]", "Bin Size [ps]");
00104             }
00105       
00106       //histograms for the non-linear correction
00107          if( 1 == fPar->uEnableCalib )
00108          {
00109             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00110             {
00111                fDnlCorr[imodule][ichan] = MakeTH1('D', Form("FPGA/tdc%d/Dnl/chan%02dDnlCorr%d",imodule,ichan,imodule),
00112                          Form("DnlSum Tdc %d channel %2d",imodule, ichan),
00113                          TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00114                          "Fine Time [bin]");
00115             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00116 
00117             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTotHistoEnable )
00118                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN/2; ichan++)
00119                   fToT[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/tot/chan%02dToT%d",imodule,ichan,imodule),
00120                     Form("ToT Tdc %d channel %2d",imodule, ichan),
00121                     30000, -150000, 150000, "ToT [ps]");
00122          } // if( 1 == fPar->uEnableCalib )
00123       
00124          if( 1 == fPar->uBitControl)
00125          {
00126             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00127             {
00128                bitcontrol[imodule][ichan] = MakeTH1('I',
00129                          Form("FPGA/tdc%d/bits%d/chan%02dBitcontrol%d",imodule,imodule,ichan,imodule),
00130                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00131                          TDC_FIFO_COARSE_CT_SHIFT, 0, TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00132                bitcontrolCoarse[imodule][ichan] = MakeTH1('I',
00133                          Form("FPGA/tdc%d/bits%dCoarse/chan%02dBitcontrol%dCoarse",imodule,imodule,ichan,imodule),
00134                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00135                          TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,
00136                          0, TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00137             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00138          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl)
00139       
00140          if( 1 == fPar->uCoarseTimeHisto )
00141          {
00142             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00143             {
00144                fCoarseTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/ct/chan%02dCoarseTime%d",imodule,ichan,imodule),
00145                        Form("CoarseTime Tdc %d channel %2d",imodule, ichan),
00146                        TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT, -0.5, (TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT)-0.5,
00147                        "Coarse Time [bin]");
00148             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00149          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00150 
00151          // Checking how diamond time relatice to trigger depend on the triggers
00152          if( -1 < fPar->iVftxReference2Channel[imodule] )
00153             fRef2TimeTriggerDep[imodule] = MakeTH2('I', Form("FPGA/tdc%d/Ref2VsTrigger%d",imodule,imodule),
00154                   Form("2nd reference (Diamond) Time to trigger depending on the active trigger, Tdc %d",imodule),
00155                   800, -395000, 5000, 16, 0, 16,
00156                   "Trigger time - 2nd reference (Diamond) Calibrated Time [ps]", "Trigger []");
00157 
00158          // If the main reference tdc is not defined or its 1st reference channel is invalid
00159          // Find first board with a 1st reference channel and then use it to compare the other boards
00160          // else compare main reference tdc to the other boards
00161          if( ( -1 == iFirstModuleWithReference1 || imodule == fPar->iMainReferenceTdc ) &&
00162                -1 < fPar->iVftxReference1Channel[imodule])
00163             iFirstModuleWithReference1 = imodule;
00164          else if( -1 < fPar->iVftxReference1Channel[imodule])
00165             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] &&
00166                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00167                fTdcResolutionRef1Check[imodule] = MakeTH1('I', Form("FPGA/Ref1Tdc%dVsTdc%d",imodule, iFirstModuleWithReference1 ),
00168                      Form("Time 1st reference signal Tdc %d against Tdc %d",imodule, iFirstModuleWithReference1),
00169                      30000, -15000, 15000,
00170                      Form("tRef1_%d - tRef1_%d [ps]", imodule, iFirstModuleWithReference1));
00171 
00172          // If the main reference tdc is not defined or its 2nd reference channel is invalid
00173          // Find first board with a 2nd reference channel and then use it to compare the other boards
00174          // else compare main reference tdc to the other boards
00175          if( ( -1 == iFirstModuleWithReference2 || imodule == fPar->iMainReferenceTdc ) &&
00176                -1 < fPar->iVftxReference2Channel[imodule])
00177             iFirstModuleWithReference2 = imodule;
00178          else if( -1 < fPar->iVftxReference2Channel[imodule] && -1 < iFirstModuleWithReference2)
00179             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] &&
00180                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00181                fTdcResolutionRef2Check[imodule] = MakeTH1('I', Form("FPGA/Ref2Tdc%dVsTdc%d",imodule, iFirstModuleWithReference2 ),
00182                      Form("Time 2nd reference (Diamond) signal Tdc %d against Tdc %d",imodule, iFirstModuleWithReference2),
00183                      30000, -15000, 15000,
00184                      Form("tref2_%d - tref2_%d [ps]", imodule, iFirstModuleWithReference2));
00185       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00186    } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00187    uInitialMbsTime   = 0;
00188    uInitialVulomSync = 0;
00189 
00190    if( 1 == fPar->uVftxCoincidenceMap )
00191    {
00192       iMapIndex = 0;
00193       for( Int_t iModule1 = 0; iModule1 < MAX_FPGA_TDC; iModule1 ++)
00194          if( 1 == fPar->uVftxCalHistosEnabled[iModule1] )
00195             for( Int_t iModule2 = iModule1; iModule2 < MAX_FPGA_TDC; iModule2 ++)
00196             {
00197                if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00198                {
00199                   TGo4Log::Info("****Vftx monitor: Error creating mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00200                         iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule1, iModule2);
00201                   break;
00202                }
00203                if( 1 == fPar->uVftxCalHistosEnabled[iModule2] )
00204                   fTdcChanStripMapping[ iMapIndex ] =
00205                            MakeTH2('I', Form("FPGA/Mapping/Mapp%d_%dVftx", iModule1, iModule2 ),
00206                                         Form("Channel during same event?, Tdc %d VS Tdc %d", iModule1, iModule2),
00207                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00208                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00209                                          Form("Channel Tdc #%d []", iModule1),
00210                                          Form("Channel Tdc #%d []", iModule2),"Events []");
00211                iMapIndex++;
00212             }
00213    } // if( 1 == fPar->uVftxCoincidenceMap )
00214 
00215    if( 1 == fPar->uEnableCalib )
00216    {
00217       if( 1 == fPar->uSingleChannelCalibFilesEnable )
00218       {
00219          TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00220          TGo4Log::Info("%s", sInfoLoading.Data() );
00221          sInfoLoading = "         ";
00222          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00223             sInfoLoading += Form("%2d ", ichan);
00224          TGo4Log::Info("%s", sInfoLoading.Data() );
00225 
00226          //define correction variables
00227          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00228          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00229 
00230          oldDir = gDirectory;
00231 
00232          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00233          {
00234             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00235                continue;
00236 
00237             sInfoLoading = Form("tdc #%2d: ",imodule );
00238             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00239             {
00240                TString sInitialCalibFileName = Form("./Calib/Tdc%02dChan%02d.root ", fPar->uVftxInitalCalIndex[imodule], ichan);
00241                TString sInitalCalibHistoName = "";
00242                fileCalibrationIn = new TFile( sInitialCalibFileName, "READ");
00243                if( kTRUE == fileCalibrationIn->IsOpen() )
00244                {
00245                   TH1* fInitialCalibHistoFromFile = 0;
00246                   sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00247                   fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHistoFromFile);
00248 
00249                   if( 0 == fInitialCalibHistoFromFile )
00250                      sInfoLoading += " 0 ";
00251                      else
00252                      {
00253                         sInfoLoading += " 1 ";
00254                         fInitialCalibHisto[imodule][ichan] = 0;
00255                         fInitialCalibHisto[imodule][ichan] = (TH1*)fInitialCalibHistoFromFile->Clone(Form("CalibSingleChanFile_tdc%02d_chan%02d", imodule, ichan));
00256                         fInitialCalibHisto[imodule][ichan]->SetDirectory( oldDir );
00257                         if( 0 != fInitialCalibHisto[imodule][ichan])
00258                         {
00259                            // Try to use initial calibration histo always
00260                            fDnlCorr[imodule][ichan]->Reset();
00261                            //set a the sum to zero before summing over all bins in one channel
00262                            iSum[imodule][ichan] = 0;
00263                            Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00264 
00265                            for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00266                            {
00267                               Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00268                                                   (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00269                               //Looking for the used bins
00270                               if( iBinContent <= 0)
00271                               {
00272                                  bincontrol[ibin] = kFALSE;
00273                               }
00274                               else if( iBinContent > 0)
00275                               {
00276                                  bincontrol[ibin] = kTRUE;
00277                               }
00278 
00279                               // build the sum of all bin content
00280                               if(bincontrol[ibin])
00281                               {
00282                       iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00283                       dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00284                               }
00285                               else
00286                               {
00287                                  if( 0 < ibin)
00288                                     dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00289                                     else dCorr[imodule][ichan][ibin]=0;
00290                               }
00291                               fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00292                            } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00293                         } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00294                      } // else of if( 0 == fInitialCalibHistoFromFile )
00295                   fileCalibrationIn->Close();
00296                } // if( kTRUE == fileCalibrationIn->IsOpen() )
00297                   else sInfoLoading += " 0 ";
00298             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00299             TGo4Log::Info("%s", sInfoLoading.Data() );
00300          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00301       } // if( 1 == uSingleChannelCalibFilesEnable )
00302       else if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00303            kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") )
00304       {
00305          // Save online ROOT directory as the File opening auto change current Dir
00306          oldDir = gDirectory;
00307 
00308          TString sInitalCalibHistoName = "";
00309          fileCalibrationIn = new TFile( fPar->sInitialCalibrationFilename, "READ");
00310 
00311          if( kTRUE == fileCalibrationIn->IsOpen() )
00312          {
00313             TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00314             TGo4Log::Info("%s", sInfoLoading.Data() );
00315             sInfoLoading = "         ";
00316             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00317                sInfoLoading += Form("%2d ", ichan);
00318             TGo4Log::Info("%s", sInfoLoading.Data() );
00319 
00320             //define correction variables
00321             Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00322             Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00323 
00324             // Temp variable to store pointer on calib histo in File
00325             TH1* fInitialCalibHistoFromFile = 0;
00326 
00327             for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00328             {
00329                if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00330                   continue;
00331 
00332                sInfoLoading = Form("tdc #%2d: ",imodule );
00333                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00334                {
00335                   fInitialCalibHistoFromFile = 0;
00336                   fInitialCalibHisto[imodule][ichan] = 0;
00337 
00338                   // Find histogram in file and store its pointer in a temp variable
00339                   sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00340                   fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHistoFromFile);
00341 
00342                   if( 0 == fInitialCalibHistoFromFile )
00343                      sInfoLoading += " 0 ";
00344                      else
00345                      {
00346                         sInfoLoading += " 1 ";
00347                         // Clone the found histo and move it to online ROOT directory instead of File
00348                         fInitialCalibHisto[imodule][ichan] = (TH1*)fInitialCalibHistoFromFile->Clone(Form("CalibHistoFile_tdc%02d_chan%02d", imodule, ichan));
00349                         fInitialCalibHisto[imodule][ichan]->SetDirectory( oldDir );
00350                      }
00351 
00352                   if( 0 != fInitialCalibHisto[imodule][ichan])
00353                   {
00354                      // Try to use initial calibration histo always
00355                      fDnlCorr[imodule][ichan]->Reset();
00356                      //set a the sum to zero before summing over all bins in one channel
00357                      iSum[imodule][ichan] = 0;
00358                      Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00359 
00360                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00361                      {
00362                         Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00363                                             (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00364                         //Looking for the used bins
00365                         if( iBinContent <= 0)
00366                         {
00367                            bincontrol[ibin] = kFALSE;
00368                         }
00369                         else if( iBinContent > 0)
00370                         {
00371                            bincontrol[ibin] = kTRUE;
00372                         }
00373 
00374                         // build the sum of all bin content
00375                         if(bincontrol[ibin])
00376                         {
00377                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00378                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00379                         }else
00380                         {
00381                            if( 0 < ibin)
00382                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00383                               else dCorr[imodule][ichan][ibin]=0;
00384                         }
00385                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00386                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00387                   } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00388                } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00389                TGo4Log::Info("%s", sInfoLoading.Data() );
00390             } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00391             // File closing and going back to online ROOT folder
00392             fileCalibrationIn->Close();
00393             gDirectory->Cd(oldDir->GetPath());
00394          } // if( kTRUE == fileCalibrationIn->IsOpen() )
00395             else
00396             {
00397                TGo4Log::Info("Could not open %s to load initial VFTX calibration, please check setting in Vftx_options.txt",
00398                                fPar->sInitialCalibrationFilename.Data() );
00399                for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00400                   for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00401                      fInitialCalibHisto[imodule][ichan] = 0;
00402             } // else of if( kTRUE == fileCalibrationIn->IsOpen() )
00403       } // if(  sInitialCalibrationFilename OK and 1 == fPar->uEnableCalib)
00404    } // if( 1 == fPar->uEnableCalib )
00405 
00406    //~ TGo4Log::Info("**** TVftxProc: Instance %s created", name );
00407 }
00408 
00409 
00410 TVftxProc::~TVftxProc()
00411 {
00412    cout << "**** TVftxProc: Delete instance " << endl;
00413    
00414    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00415         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00416         1 == fPar->uEnableCalib &&
00417         kTRUE == fileCalibrationIn->IsOpen() )
00418       fileCalibrationIn->Close();
00419       
00420    if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00421    {
00422       TTimeStamp timeCurrent;
00423       oldDir = gDirectory;
00424       TString sCalibOutFilename = Form("./VftxCalibHistos_%u_%u.root", timeCurrent.GetDate( kFALSE), timeCurrent.GetTime( kFALSE) );
00425       TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE", 
00426                                             Form("Calibration Data for VFTX, saved from analysis on %s", timeCurrent.AsString("lc") ), 
00427                                             9);
00428       if( kTRUE == fileCalibrationOut->IsOpen() )
00429       {
00430          sCalibOutFilename += ":/";
00431          gDirectory->Cd(sCalibOutFilename);
00432          TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00433          TGo4Log::Info("%s", sInfoSaving.Data() );
00434          sInfoSaving = "         ";
00435          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00436             sInfoSaving += Form("%2d ", ichan);
00437          TGo4Log::Info("%s", sInfoSaving.Data() );
00438          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00439          {
00440             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00441                continue;
00442             sInfoSaving = Form("tdc #%2d: ",imodule );
00443             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00444             {
00445                if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00446                {
00447                fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00448                                                  TObject::kOverwrite);
00449                sInfoSaving += " 1 ";
00450                }
00451                   else sInfoSaving += " 0 ";
00452             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00453             TGo4Log::Info("%s", sInfoSaving.Data() );
00454          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00455          //fileCalibrationOut->Write("",TObject::kOverwrite);
00456          fileCalibrationOut->Close();
00457          TGo4Log::Info("Calibration data saved in %s", sCalibOutFilename.Data() );
00458       } // if( kTRUE == fileCalibrationOut->IsOpen() )
00459          else TGo4Log::Warn("Error when deleting TVftxProc: Unable to open root file %s to save calibration data, please check settings",
00460                               sCalibOutFilename.Data() );
00461       gDirectory->Cd(oldDir->GetPath());
00462    } // if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00463    if( ( 1 == fPar->uSingleChannelCalibFilesOutput || 2 == fPar->uSingleChannelCalibFilesOutput )
00464          && 1 == fPar->uEnableCalib )
00465    {
00466       TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00467       TGo4Log::Info("%s", sInfoSaving.Data() );
00468       sInfoSaving = "         ";
00469       for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00470          sInfoSaving += Form("%2d ", ichan);
00471       TGo4Log::Info("%s", sInfoSaving.Data() );
00472 
00473       oldDir = gDirectory;
00474       for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00475       {
00476          if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00477             continue;
00478          sInfoSaving = Form("tdc #%2d: ",imodule );
00479          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00480          {
00481             TString sCalibOutFilename = Form("./Calib/Tdc%02dChan%02d.root", imodule, ichan );
00482             TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE",
00483                                                   Form("Calibration Data for VFTX %02d channel %02d", imodule, ichan ),
00484                                                   9);
00485             if( kTRUE == fileCalibrationOut->IsOpen() )
00486             {
00487                sCalibOutFilename += ":/";
00488                gDirectory->Cd(sCalibOutFilename);
00489                if( 1 == fPar->uSingleChannelCalibFilesOutput || 0 == fInitialCalibHisto[imodule][ichan] )
00490                {
00491                   // New Calibration histo using only new data
00492                   if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00493                   {
00494                      fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00495                                                        TObject::kOverwrite);
00496                      sInfoSaving += " 1 ";
00497                   } // if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00498                      else sInfoSaving += " 0 ";
00499                } // if( 1 == fPar->uSingleChannelCalibFilesOutput )
00500                else
00501                {
00502                   // Try to update old calibration histo with new data
00503                   if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00504                      fInitialCalibHisto[imodule][ichan]->Add( fFineTime[imodule][ichan] );
00505                   fInitialCalibHisto[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00506                                                     TObject::kOverwrite);
00507                   sInfoSaving += " 1 ";
00508                } // else of if( 1 == fPar->uSingleChannelCalibFilesOutput )
00509             } // if( kTRUE == fileCalibrationOut->IsOpen() )
00510                else sInfoSaving += " 0 ";
00511             //fileCalibrationOut->Write("",TObject::kOverwrite);
00512             fileCalibrationOut->Close();
00513             gDirectory->Cd(oldDir->GetPath());
00514          } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00515          TGo4Log::Info("%s", sInfoSaving.Data() );
00516       } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00517       gDirectory->Cd(oldDir->GetPath());
00518    } // if( 1 == fPar->uSingleChannelCalibFilesOutput && 1 == fPar->uEnableCalib )
00519 }
00520 
00521 void TVftxProc::InitEvent(TGo4EventElement* outevnt)
00522 {
00523    // first assign input event:
00524    // since input event object is never discarded within processor lifetime,
00525    // we just search for subevent by name once to speed up processing
00526 
00527    //cout << "VftxProc Init Event " <<  endl;
00528 
00529    if(fCrateInputEvent==0)
00530    {
00531       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(GetInputEvent());
00532       if(btevent)
00533       {
00534          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(btevent->GetSubEvent("MBSCRATE"));
00535          fTriglogInputEvent=dynamic_cast<TTriglogEvent*>(btevent->GetSubEvent("TRIGLOG"));
00536       }
00537       else
00538       {
00539          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(GetInputEvent());
00540       }
00541       if(fCrateInputEvent==0) {
00542         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event is not a TMbsCrateEvent!!! STOP GO4");
00543       }
00544       if(fTriglogInputEvent==0) {
00545         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event has no TTriglogEvent!!! STOP GO4");
00546       }
00547    }
00548    // then assign output event
00549 
00550    // since output event object is never discarded within processor lifetime,
00551    // we just search for subevent by name once to speed up processing
00552    if(fOutputEvent==0)
00553    {
00554       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(outevnt);
00555       if(btevent)
00556       {
00557          fOutputEvent=dynamic_cast<TVftxEvent*>(btevent->GetSubEvent("VFTX"));
00558       }
00559       else
00560       {
00561 
00562          fOutputEvent= dynamic_cast<TVftxEvent*>(outevnt);
00563       }
00564       if(fOutputEvent==0) {
00565         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: output event is not a TVftxEvent!!! STOP GO4");
00566       }
00567       else {
00568          //     BuildEvent(dynamic_cast<TGo4MbsSubEvent*>(btevent->GetSubEvent("MBSCRATE")));
00569       }
00570    }
00571 }
00572 
00573 void TVftxProc::FinalizeEvent()
00574 {
00575   //   cout << "**** TVftxProc: Finalize Event " << endl;
00576    if (fCrateInputEvent->IsValid()) 
00577    {
00578       // variables
00579       Int_t imodule = 0;
00580       Int_t iEvtSizeHeader1[MAX_FPGA_TDC];
00581       Int_t iEvtSizeHeader2[MAX_FPGA_TDC];
00582       for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++) 
00583       {
00584          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00585          {
00586             iFirstTime[imodule][ichan]     = -1;
00587             iFirstCoarse[imodule][ichan]   = -1;
00588             iFirstFine[imodule][ichan]     = -1;
00589             dFirstTimecorr[imodule][ichan] = -1;
00590             dFirstFineTimecorr[imodule][ichan] = -1;
00591             iLastTime[imodule][ichan]    = 0;
00592             for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00593             {
00594                dTimeCorr[imodule][ichan][imul] = -1;
00595                dFineTimeCorr[imodule][ichan][imul] = -1;
00596             }
00597             uTotalMultiplicity[imodule][ichan]    = 0;
00598          }
00599          iTriggerTime[imodule] = 0;
00600       }
00601       imodule = 0;
00602       // fill histograms    
00603       for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++) {
00604          if( 0 == fPar->uVftxCalHistosEnabled[fpga] )
00605             continue;
00606 
00607          unsigned num_hits = fCrateInputEvent->fFPGA[fpga].size(); // per tdc
00608          imodule  = fpga;
00609          
00610          if( 0 == num_hits && 0 == fCrateInputEvent->fFPGAHEAD[fpga].size() ) // check if fpga data are there
00611             continue;
00612          iEvtSizeHeader1[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).nr_data;
00613          iEvtSizeHeader2[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_nd;
00614          iTriggerTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00615          headTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00616          
00617          if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00618          {
00619             fEventSizeHeader1[imodule]->Fill( iEvtSizeHeader1[imodule] );
00620             fEventSizeHeader2[imodule]->Fill( iEvtSizeHeader2[imodule] );
00621             fTriggerType[imodule]->Fill(fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_tt);
00622             fTriggerTime[imodule]->Fill( iTriggerTime[imodule] );
00623          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00624          
00625          (fOutputEvent->fVftxBoards[imodule]).iTriggerTime = headTime[imodule];
00626          
00627          for(unsigned i = 0; i<num_hits; i++) 
00628          {
00629             uint32_t ichan =  fCrateInputEvent->fFPGA[fpga].at(i).ch_ix;
00630             uint32_t bFutureBit = fCrateInputEvent->fFPGA[fpga].at(i).future_bit;
00631             int32_t iCoarseCounter =  fCrateInputEvent->fFPGA[fpga].at(i).coarse_ct;
00632             int32_t iFineCounter =  fCrateInputEvent->fFPGA[fpga].at(i).ch_tim;
00633 
00634             // for given module add data
00635             Int_t channel=ichan; 
00636                
00637             if( (imodule >= 0) && (imodule < MAX_FPGA_TDC) && 
00638                 (channel >= 0) && (channel < FPGA_TDC_NBCHAN) )
00639             {
00640 
00641                if( ((fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] < TVftxBoardData::TVftxBoardData::MaxMult) )
00642                {
00643                   (fOutputEvent->fVftxBoards[imodule]).iFineTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]   = iFineCounter;
00644                   (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ] = iCoarseCounter;
00645                   (fOutputEvent->fVftxBoards[imodule]).uFutureBit[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]  = bFutureBit;
00646                   (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel]++;
00647                }
00648                uTotalMultiplicity[imodule][channel]++;
00649             }
00650                else continue;
00651 
00652             //Calculation of non-linear Correction
00653             if( 0 == uInitialMbsTime )
00654             {
00655                uInitialMbsTime   = fTriglogInputEvent->fMbsTimeSecs;
00656                uInitialVulomSync = fTriglogInputEvent->fVulomSyncNumber;
00657             }
00658             if( 1 == fPar->uFineHistEnable )
00659             {
00660                if( 0 == fFineTime[imodule][ichan]->GetEntries() )
00661                   iNbHitsForCalib[imodule][ichan] = 0;
00662                   
00663                fFineTime[imodule][ichan]->Fill(iFineCounter);
00664                
00665                iNbHitsForCalib[imodule][ichan] ++;
00666                if( fPar->iMinNbHitsCalib == iNbHitsForCalib[imodule][ichan] )
00667                   TGo4Log::Info("FPGA TDC: Calibration data ok for module %d channel %d, after %d events", imodule, ichan, fTriglogInputEvent->fVulomSyncNumber - uInitialVulomSync);
00668             }
00669             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable )
00670                fFineTimeEvo[imodule][ichan]->Fill( UInt_t((fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/3600), iFineCounter);
00671 
00672             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00673                fCoarseTime[imodule][ichan]->Fill(iCoarseCounter);
00674 
00675             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00676             {
00677                for (uint16_t ibit = 0; ibit <= 9; ibit++) 
00678                   if ((iFineCounter >> ibit) & 0x1) bitcontrol[imodule][ichan]->Fill( ibit );
00679                for (uint16_t ibit = 0; ibit <= 15; ibit++) 
00680                   if ((iCoarseCounter >> ibit) & 0x1) bitcontrolCoarse[imodule][ichan]->Fill( ibit );
00681             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00682 
00683             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00684             {
00685                fChanUsage[imodule]->Fill(ichan);
00686                if (bFutureBit) fChanFuture[imodule]->Fill(ichan);
00687             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00688 
00689             if (iLastTime[imodule][ichan])
00690             {
00691                if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00692                   fChanDouble[imodule]->Fill(ichan);
00693             }
00694             else
00695             {
00696                iFirstCoarse[imodule][ichan] = iCoarseCounter;
00697                iFirstFine[imodule][ichan]   = iFineCounter;
00698                iFirstTime[imodule][ichan]   = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)
00699                                                + iFineCounter; // Modif PAL to re-add the coarse counter shift
00700             }
00701 
00702             iLastTime[imodule][ichan] = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)  + iFineCounter;
00703          } // for(unsigned i = 0; i<num_hits; i++)
00704             
00705       } // for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++)
00706       
00707       if( 1 == fPar->uEnableCalib )
00708       {
00709          //define correction variables
00710          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00711          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00712         
00713          for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00714          {
00715             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00716                continue;
00717 
00718             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00719             {
00720                // cout<<" Test Corr Tdc "<<imodule<<" chan "<<ichan<<endl;
00721                if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]  &&
00722                    -1 <  fPar->iMinNbHitsCalib)
00723                {
00724                   if(// iNbHitsForCalib[imodule][ichan]< (2*fPar->iMinNbHitsCalib) ||
00725                     0 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00726                   {
00727                      fDnlCorr[imodule][ichan]->Reset();
00728                      //set a the sum to zero before summing over all bins in one channel
00729                      iSum[imodule][ichan] = 0;
00730                      Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() );
00731                      
00732                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00733                      {
00734                         Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1));
00735                         //Looking for the used bins
00736                         if( iBinContent <= 0)
00737                         {
00738                            bincontrol[ibin] = kFALSE;
00739                         }
00740                         else if( iBinContent > 0)
00741                         {
00742                            bincontrol[ibin] = kTRUE;
00743                         }
00744                            
00745                         // build the sum of all bin content
00746                         if(bincontrol[ibin])
00747                         {
00748                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00749                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00750                 if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00751                     0 == iNbHitsForCalib[imodule][ichan]%10000 )
00752                   fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00753                               CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00754                         }else
00755                         {
00756                            if( 0 < ibin)
00757                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00758                               else dCorr[imodule][ichan][ibin]=0;
00759                         }      
00760                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00761                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00762                   } // if( iNbHitsForCalib[imodule][ichan]<1e6 || 0 == iNbHitsForCalib[imodule][ichan]%40000 )
00763                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00764                   else if( -1 < fPar->iMinNbHitsCalib )
00765                   {
00766                      // Try to use initial calibration histo as long as under 
00767                      // the minimal number of hits in calibration
00768                      if( 0 != fInitialCalibHisto[imodule][ichan] &&
00769                          fPar->iMinNbHitsCalib - 1 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00770                      {
00771                         fDnlCorr[imodule][ichan]->Reset();
00772                         //set a the sum to zero before summing over all bins in one channel
00773                         iSum[imodule][ichan] = 0;
00774                         Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() ) + 
00775                                                         (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00776                         
00777                         for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00778                         {
00779                            Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00780                                                (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00781                            //Looking for the used bins
00782                            if( iBinContent <= 0)
00783                            {
00784                               bincontrol[ibin] = kFALSE;
00785                            }
00786                            else if( iBinContent > 0)
00787                            {
00788                               bincontrol[ibin] = kTRUE;
00789                            }
00790                               
00791                            // build the sum of all bin content
00792                            if(bincontrol[ibin])
00793                            {
00794                    iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00795                    dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00796                    if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00797                          9999 == iNbHitsForCalib[imodule][ichan]%10000 )
00798                      fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00799                                  CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00800                            }else
00801                            {
00802                               if( 0 < ibin)
00803                                  dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00804                                  else dCorr[imodule][ichan][ibin]=0;
00805                            }      
00806                            fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00807                         } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00808                      } //  if( 0 != fInitialCalibHisto[imodule][ichan] )
00809                   } // else of else if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00810                
00811                if( ( -1<fPar->iMinNbHitsCalib && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]) ||
00812                    0 != fInitialCalibHisto[imodule][ichan] )
00813                {
00814                   if( 0<=iFirstCoarse[imodule][ichan] || 0<=iFirstFine[imodule][ichan] )
00815                   {
00816           dFirstTimecorr[imodule][ichan] = iFirstCoarse[imodule][ichan]*CLOCK_TIME
00817                    +  (1 - dCorr[imodule][ichan][iFirstFine[imodule][ichan]])*CLOCK_TIME;
00818                    dFirstFineTimecorr[imodule][ichan] = dCorr[imodule][ichan][iFirstFine[imodule][ichan]]*CLOCK_TIME;  
00819                   }  
00820                   for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00821                      if( 0<=(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul] || 
00822                          0<=(fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul])
00823                      {
00824                         dTimeCorr[imodule][ichan][imul] = (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul]*CLOCK_TIME
00825                             +  (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME; 
00826                         dFineTimeCorr[imodule][ichan][imul] = (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME;
00827                         
00828                         // Fill it in output event
00829                         (fOutputEvent->fVftxBoards[imodule]).dTimeCorr[ichan][imul]     = dTimeCorr[imodule][ichan][imul];
00830                         (fOutputEvent->fVftxBoards[imodule]).dFineTimeCorr[ichan][imul] = dFineTimeCorr[imodule][ichan][imul];
00831                      } // if( iFineTime ok || iCoarseTime ok)
00832                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])
00833                
00834             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00835                
00836             //Compare corrected time with trigger time 
00837             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00838             {
00839 #if defined(VERSION_VFTX) || defined(VERSION_VFTX_28) // 1 TDC mode, chan = Time, chan +1 = Tot
00840                /*
00841                Double_t dTimeToTrigger[FPGA_TDC_NBCHAN];
00842                Double_t dToT[FPGA_TDC_NBCHAN];
00843                for( Int_t ichan = 0; ichan < FPGA_TDC_NBCHAN; ichan ++)
00844                {
00845                   if( 1 == fPar->uTimeHistEnable && 
00846                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])&&
00847                       0 < iFirstTime[imodule][ichan] )
00848                   {
00849                      dTimeToTrigger[ichan] = dFirstTimecorr[imodule][ichan] - iTriggerTime[imodule]*CLOCK_TIME;
00850                      if( 1000 < iFirstCoarse[imodule][ichan] - iTriggerTime[imodule])
00851                         dTimeToTrigger[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00852                      if( iFirstCoarse[imodule][ichan] - iTriggerTime[imodule] < -1000 )
00853                         dTimeToTrigger[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00854                      fTime[imodule][ichan]->Fill( dTimeToTrigger[ichan] );
00855                   }
00856                   if( 1 == fPar->uTotHistoEnable && ichan < FPGA_TDC_NBCHAN/2 )
00857                      if( 0 < iFirstTime[imodule][ichan*2] && 0 < iFirstTime[imodule][ichan*2+1] &&
00858                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2]   || 0 != fInitialCalibHisto[imodule][ichan*2]  )&&
00859                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2+1] || 0 != fInitialCalibHisto[imodule][ichan*2+1]) )
00860                      {
00861                         dToT[ichan] =  dFirstTimecorr[imodule][ichan*2] -  dFirstTimecorr[imodule][ichan*2+1] ;
00862                         if( 1000 < iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] )
00863                            dToT[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00864                         if( iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] < -1000 )
00865                            dToT[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00866                         fToT[imodule][ichan]->Fill(dToT[ichan]);
00867                      } // if( 1 == fPar->uTotHistoEnable && .... )
00868                }
00869                */
00870 #else
00871                if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][0])
00872                   fTime[imodule][0]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME - dFirstTimecorr[imodule][0]);
00873                if( 1 == fPar->uTotHistoEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0]
00874                   && fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00875                   fToT[0]->Fill(((Double_t)iTriggerTime[0]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[0][0] 
00876                              - (((Double_t)iTriggerTime[1]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[1][0]));
00877                Double_t dToT[FPGA_TDC_NBCHAN];
00878                for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00879                {
00880                   if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00881                      fTime[imodule][ichan]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME
00882                                                   - dFirstTimecorr[imodule][ichan]);
00883                   if( 1 == fPar->uTotHistoEnable && 
00884                       0 < iFirstTime[0][ichan] && 0 < iFirstTime[1][ichan] &&
00885                       0 < iFirstTime[0][0]     && 0 < iFirstTime[1][0]  && 
00886                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00887                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][1] &&
00888                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
00889                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
00890                   {
00891                       dToT[ichan] = (iTriggerTime[0]*(Double_t)CLOCK_TIME )  - dFirstTimecorr[0][ichan] 
00892                         - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][ichan])
00893                         - ( (iTriggerTime[0]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[0][0] 
00894                        - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][0])) ;
00895                      fToT[ichan]->Fill(dToT[ichan]);
00896                   } // if( 1 == fPar->uTotHistoEnable && .... )
00897                } // for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
00898 #endif
00899             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00900          } // for(  imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00901 
00902          // Fill the output event
00903          for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
00904          {
00905             if( 0 == fPar->uVftxCalHistosEnabled[iModule] )
00906                continue;
00907 
00908             Double_t dTimeToTrigger;
00909             Double_t dToT;
00910             for(Int_t iChan=0; iChan < FPGA_TDC_NBCHAN; iChan++)
00911             {
00912                for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
00913                {
00914                   if( 1 == fPar->uTimeHistEnable &&
00915                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan] || 0 != fInitialCalibHisto[iModule][iChan])&&
00916                       0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]  )
00917                   {
00918                      dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
00919                                      - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
00920                      if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
00921                         dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00922                      if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1000 )
00923                         dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00924                      fTime[iModule][iChan]->Fill( dTimeToTrigger );
00925 
00926                      if( 1 == fPar->uTimeHistSinglesEnable && 0 == iHit &&
00927                            1 == (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ])
00928                      {
00929                         Double_t dTimeToTriggerSingle =
00930                                           (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
00931                                         - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
00932                         if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
00933                            dTimeToTriggerSingle -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00934                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit] - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1000 )
00935                            dTimeToTriggerSingle += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00936                         fTimeSingles[iModule][iChan]->Fill( dTimeToTriggerSingle );
00937                      }
00938 
00939                      if( 1 == fPar->uMultiHitsDistanceHistoEnable)
00940                         if( 0 < iHit && iHit < TVftxBoardData::MaxMult +1)
00941                         {
00942                            Double_t dTimeToPreviousHit = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
00943                                                        - (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit - 1];
00944                            if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
00945                                     - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit - 1])
00946                               dTimeToPreviousHit -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00947                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
00948                              - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit - 1] < -1000 )
00949                               dTimeToPreviousHit += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00950                            fMultihitsDistance[iModule][iChan]->Fill( dTimeToPreviousHit, iHit);
00951                         } // if( 0 < iHit && iHit < TVftxBoardData::MaxMult +1)
00952                   } // if hit is ok and calibrated
00953                } // for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
00954                if( 1 == fPar->uTotHistoEnable && iChan < FPGA_TDC_NBCHAN/2 )
00955                   for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2 ] &&
00956                                        iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2+1 ]; iHit++)
00957                   {
00958                      if( 0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit] &&
00959                            0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit] &&
00960                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2]   || 0 != fInitialCalibHisto[iModule][iChan*2]  )&&
00961                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2+1] || 0 != fInitialCalibHisto[iModule][iChan*2+1]) )
00962                      {
00963                         dToT =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit]
00964                                      -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit];
00965                         if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
00966                                    - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] )
00967                            dToT -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00968                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
00969                             - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] < -1000 )
00970                            dToT += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
00971                         fToT[iModule][iChan]->Fill(dToT);
00972                      } // if both edges ok and calibrated
00973                   } // for all hits until one edge is missing
00974 
00975                // Go back to index for VFTX internal map
00976                if( 1 == fPar->uVftxCoincidenceMap )
00977                   iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
00978                            - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2;
00979 
00980                if( 1 == fPar->uVftxCalHistosEnabled[iModule]  &&
00981                    0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan] )
00982                {
00983                   fChanEvents[iModule]->Fill(iChan);
00984                   if( 1 == fPar->uVftxCoincidenceMap )
00985                   {
00986                      if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00987                      {
00988                         TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00989                               iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule);
00990                         return;
00991                      } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00992                      for(Int_t iChan2=iChan+1; iChan2<FPGA_TDC_NBCHAN; iChan2++)
00993                         if( 1 == fPar->uVftxCalHistosEnabled[iModule] && 0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan2] )
00994                         {
00995                            fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
00996                         }
00997 
00998                      for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
00999                      {
01000                         // Find index for corresponding VFTX against VFTX map
01001                         iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
01002                                  - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2
01003                                  + (iModule2 - iModule);
01004                         if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01005                         {
01006                            TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
01007                                  iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule2);
01008                            return;
01009                         } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01010                         for(Int_t iChan2=0; iChan2<FPGA_TDC_NBCHAN; iChan2++)
01011                            if( 1 == fPar->uVftxCalHistosEnabled[iModule2] && 0<(fOutputEvent->fVftxBoards[iModule2]).iMultiplicity[iChan2] )
01012                            {
01013                               fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
01014                            }
01015                      } // for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
01016                   } // if( 1 == fPar->uVftxCoincidenceMap )
01017                } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && chan1 there)
01018 
01019                if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
01020                   fChanMultip[iModule]->Fill(iChan, uTotalMultiplicity[iModule][iChan] );
01021             } // for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++)
01022          } //  for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01023 
01024          // Checking how diamond time relatice to trigger depend on the triggers
01025          Double_t dRef2TimeToTrigger = 0.0;
01026          for(Int_t iTrigger = 0; iTrigger<16; iTrigger++)
01027             if( 1 == ((fTriglogInputEvent->fVulomTriggerPattern>>iTrigger) & 0x1) )
01028                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01029                   if( -1 < fPar->iVftxReference2Channel[iModule] )
01030                      for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference2Channel[iModule] ]; iHit++)
01031                {
01032                   dRef2TimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][iHit]
01033                                           - iTriggerTime[iModule]*CLOCK_TIME;
01034                   if( 1000 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxReference2Channel[iModule]][iHit] - iTriggerTime[iModule])
01035                      dRef2TimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01036                   if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxReference2Channel[iModule]][iHit] - iTriggerTime[iModule] < -1000 )
01037                      dRef2TimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01038                   fRef2TimeTriggerDep[iModule]->Fill( dRef2TimeToTrigger, iTrigger );
01039                } //  for Trigger, Module, Hit, if Trigger there and Diamond channel of the module defined
01040 
01041          if( -1 < iFirstModuleWithReference2)
01042             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] &&
01043                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).iMultiplicity[fPar->iVftxReference2Channel[iFirstModuleWithReference2]] )
01044                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01045                   if( iModule != iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01046                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference2Channel[iModule]] )
01047                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][0] &&
01048                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).dTimeCorr[fPar->iVftxReference2Channel[iFirstModuleWithReference2]][0] )
01049                      fTdcResolutionRef2Check[iModule]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][0] -
01050                                 (fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).dTimeCorr[fPar->iVftxReference2Channel[iFirstModuleWithReference2]][0] );
01051 
01052          if( -1 < iFirstModuleWithReference1)
01053             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] &&
01054                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).iMultiplicity[fPar->iVftxReference1Channel[iFirstModuleWithReference1]] )
01055                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01056                   if( iModule != iFirstModuleWithReference1 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference1Channel[iModule] )
01057                   {
01058                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference1Channel[iModule]] )
01059                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference1Channel[iModule]][0] &&
01060                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).dTimeCorr[fPar->iVftxReference1Channel[iFirstModuleWithReference1]][0] )
01061                      fTdcResolutionRef1Check[iModule]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference1Channel[iModule]][0] -
01062                                 (fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).dTimeCorr[fPar->iVftxReference1Channel[iFirstModuleWithReference1]][0] );
01063                   } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && fPar->iVftxReference1Channel[iModule] )
01064 
01065          // Automatic detection of the 1 clock cycle offset between TDcs due to
01066          // uncertainty on the exact reset time on startup
01067          if( 1 == fPar->uAutomaticOffsetEnable )
01068          {
01069             if( -1 < iFirstModuleWithReference1)
01070             {
01071                if( iFirstModuleWithReference1 == iFirstModuleWithReference2 &&
01072                    1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1])
01073                {
01074                   // Use both reference signals for more safety
01075                   for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01076                      if( 1 == fPar->uVftxCalHistosEnabled[iModule] && iModule != iFirstModuleWithReference1 &&
01077                          -1 < fPar->iVftxReference1Channel[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01078                         if( 5000 < ( fTdcResolutionRef1Check[iModule]->GetEntries() + fTdcResolutionRef2Check[iModule]->GetEntries() ) )
01079                         {
01080                            if( fTdcResolutionRef1Check[iModule]->GetMean() < - 2500 &&
01081                                fTdcResolutionRef2Check[iModule]->GetMean() < - 2500 )
01082                               fPar->iAutomaticTdcOffset[iModule] = 1;
01083                            else if( 2500 < fTdcResolutionRef1Check[iModule]->GetMean() &&
01084                                      2500 < fTdcResolutionRef2Check[iModule]->GetMean() )
01085                               fPar->iAutomaticTdcOffset[iModule] = -1;
01086                         } // if( 5000 < ( fTdcResolutionRef1Check[iModule-1]->GetEntries() + fTdcResolutionRef2Check[iModule-1]->GetEntries() ) )
01087                } // if( -1 < iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1])
01088                   else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01089                   {
01090                      // Check position of the peak in reference 1 signal difference between TDCs
01091                      for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01092                         if( iModule != iFirstModuleWithReference1 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference1Channel[iModule] )
01093                            if( 5000 < fTdcResolutionRef1Check[iModule]->GetEntries() )
01094                            {
01095                               if( fTdcResolutionRef1Check[iModule]->GetMean() < - 2500 )
01096                                  fPar->iAutomaticTdcOffset[iModule] = 1;
01097                               else if( 2500 < fTdcResolutionRef1Check[iModule]->GetMean() )
01098                                  fPar->iAutomaticTdcOffset[iModule] = -1;
01099                            } // if( 5000 < fTdcResolutionRef1Check[iModule-1]->GetEntries() )
01100                   } // else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01101             } // if( -1 < iFirstModuleWithReference1)
01102                else if( -1 < iFirstModuleWithReference2)
01103                {
01104                   if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] )
01105                   {
01106                      // Check position of the peak in reference 2 signal difference between TDCs
01107                      for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01108                         if( iModule != iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01109                            if( 5000 < fTdcResolutionRef2Check[iModule]->GetEntries() )
01110                            {
01111                               if( fTdcResolutionRef2Check[iModule]->GetMean() < - 2500 )
01112                                  fPar->iAutomaticTdcOffset[iModule] = 1;
01113                               else if( 2500 < fTdcResolutionRef2Check[iModule]->GetMean() )
01114                                  fPar->iAutomaticTdcOffset[iModule] = -1;
01115                            } // if( 5000 < fTdcResolutionRef1Check[iModule-1]->GetEntries() )
01116                   } // else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01117                } // else if( -1 < iFirstModuleWithReference2) of if( -1 < iFirstModuleWithReference1)
01118          } // if( 1 == fPar->uAutomaticOffsetEnable )
01119 
01120          fOutputEvent->SetValid(kTRUE);
01121       } // if( 1 == fPar->uEnableCalib )
01122          else
01123          {
01124             if( 1 == fPar->uTimeHistEnable )
01125                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
01126                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
01127                      for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++) 
01128                         for( Int_t iMul = 0; iMul< TVftxBoardData::MaxMult; iMul++) 
01129                         { 
01130                            if( -1 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul] )
01131                               fTime[iModule][iChan]->Fill(
01132                                     (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul]
01133                                             - iTriggerTime[iModule]  );
01134                         }
01135          }// else of if( 1 == fPar->uEnableCalib )
01136       fOutputEvent->SetValid(kTRUE);
01137    } //  IsValid
01138    return;
01139 }