beamtime/tof-tdctest/go4/VFTX/TVftxParam.cxx (r4864/r4727)

Go to the documentation of this file.

/* Generated by Together */

#include "TVftxParam.h"

#include "TGo4Version.h"
#if __GO4BUILDVERSION__ > 40502
   #include "go4iostream.h"
#else
   #include "Riostream.h"
#endif
 
// define default values
#define DEBUG_OPTION              0
#define CALIB_HISTOS_ENABLE       0
#define REFERENCE_CHANNEL        -1
#define MAIN_REFERENCE_TDC       -1
#define DIAMOND_CHANNEL          -1
#define COINCIDENCE_MAPPING       0
#define BIT_CONTROL               0
#define FINE_TIME_HISTO_ENABLE    0
#define COARSE_TIME_HIST_ENABLE   0
#define CALIBRATION_ENABLE        0
#define MIN_NB_HITS_CALIB      5000
#define INITIAL_CAL_FILENAME      ""
#define CALIBRATION_OUT_ENABLE    0
#define TIME_HISTO_ENABLE         0
#define TIME_HISTO_SINGLES_ENABLE 0
#define TOT_HISTO_ENABLE          0
#define MULTI_DIST_HISTO_ENABLE   0

#define TDC_OFFSET                0
#define MANUAL_TDC_OFFSET         0
#define AUTO_TDC_OFFSET_DET       0
#define USE_COARSE_CORR_TIME      0

#define SINGLE_CHAN_CALIB_INPUT   0
#define SINGLE_CHAN_CALIB_OUTPUT  0

#define BOARD_TO_SLOT            -1
#define TIME_OFFSET_CALIB_ENA     0
#define TIME_OFFSET               0.0
#define TOT_CALIB_ENABLE          0
#define TOT_OFFSET                0.0

TVftxParam::TVftxParam(const char* name) : TGo4Parameter(name)
{
   ReadOptions();
}

//***********************************************************
TVftxParam::~TVftxParam()
{
}

Bool_t TVftxParam::ReadOptions(){
   // Loading default values
   uDebug           = DEBUG_OPTION;
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      uVftxCalHistosEnabled[iIndexVftx] = CALIB_HISTOS_ENABLE;
      iVftxReference1Channel[iIndexVftx] = REFERENCE_CHANNEL;
      iVftxReference2Channel[iIndexVftx] = DIAMOND_CHANNEL;
   }
   iMainReferenceTdc = MAIN_REFERENCE_TDC;
   uVftxCoincidenceMap = COINCIDENCE_MAPPING;
   uBitControl      = BIT_CONTROL;
   uFineHistEnable  = FINE_TIME_HISTO_ENABLE;
   uCoarseTimeHisto = COARSE_TIME_HIST_ENABLE; 
   uEnableCalib     = CALIBRATION_ENABLE;
   iMinNbHitsCalib  = MIN_NB_HITS_CALIB;
   sInitialCalibrationFilename = INITIAL_CAL_FILENAME;
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      uVftxInitalCalIndex[iIndexVftx] = iIndexVftx;
   uEnableCalibOutput = CALIBRATION_OUT_ENABLE;
   uTimeHistEnable  = TIME_HISTO_ENABLE;
   uTimeHistSinglesEnable = TIME_HISTO_SINGLES_ENABLE;
   uTotHistoEnable  = TOT_HISTO_ENABLE;
   uMultiHitsDistanceHistoEnable = MULTI_DIST_HISTO_ENABLE;

   uTdcOffsetEnable       = TDC_OFFSET;
   uManualTdcOffsetEnable = MANUAL_TDC_OFFSET;
   uAutomaticOffsetEnable = AUTO_TDC_OFFSET_DET;
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      iAutomaticTdcOffset[iIndexVftx] = 0;
   
   uUseCoarseCorrectedTime = USE_COARSE_CORR_TIME;

   uSingleChannelCalibFilesEnable = SINGLE_CHAN_CALIB_INPUT;
   uSingleChannelCalibFilesOutput = SINGLE_CHAN_CALIB_OUTPUT;

   uEnableTimeOffsetCalibration = TIME_OFFSET_CALIB_ENA; // Enable/disable time offset calibration
   uEnableTotCalibration = TOT_CALIB_ENABLE;             // Enable/disable tot calibration
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      iVftxBoardIndex[iIndexVftx] = BOARD_TO_SLOT;     // No Online Change - Tdc hardware board #Y in slot/data #X
      for( Int_t iChannel = 0; iChannel < FPGA_TDC_NBCHAN/2; iChannel++)
      {
         dTimeOffset[iIndexVftx][iChannel] = TIME_OFFSET; // No Online Change - Time offset per channel, depends on TDC board, not TDC slot!!!!!
         dTotOffset[iIndexVftx][iChannel] = TOT_OFFSET; // No Online Change - ToT offset per channel, depends on TDC board, not TDC slot!!!!!
      } // for( Int_t iChannel = 0; iChannel < FPGA_TDC_NBCHAN/2; iChannel++)
   } // for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   for( Int_t iChannel = 0; iChannel < FPGA_TDC_NBCHAN/2; iChannel++)
   {
      dMeanTimeOffset[iChannel] = TIME_OFFSET; // No Online Change - Time offset per channel, independent of TDC board, this is a mean value!!!!!
      dMeanTotOffset[iChannel] = TOT_OFFSET; // No Online Change - ToT offset per channel, independent of TDC board, this is a mean value!!!!!
   } // for( Int_t iChannel = 0; iChannel < FPGA_TDC_NBCHAN/2; iChannel++)

   // Try to read the option filename from the general option files text file
   TString sOptionFileName = "./Vftx_options.txt";
   Bool_t bFilenameFound = kFALSE;
   fstream optionFilenameFile("./Option_files.txt", ios::in);
   // Testing if the file does exist. If not I use default values
   if( optionFilenameFile.fail() == true)
   {
      cout<<"************************************************************************"<<endl;
      cout<<" File with option filename for VFTX not found: using the default value ";
      cout<<sOptionFileName<<endl;
   } // if( optionFilenameFile.fail() == true)
      else
      {
         TString line;

         // Goes through all lines
         while( !optionFilenameFile.eof() )
         {
           line.ReadLine(optionFilenameFile, kFALSE); // Read a line of the option file and set the iterator automatically to the next line

           if(line(0) == '#' || line(0) == '*'||
               (line(0) == '/' && line(1) == '/') )
           {
              //Comment in the text file
              ;
           }
           else if(line.Contains("vftxcalib")==kTRUE)
           {
              sOptionFileName = ((TString)line(11, line.Sizeof()-11 ));
              cout<<"************************************************************************"<<endl;
              cout<<"Using "<<sOptionFileName<<" as source for the options of Vftx step"<<endl;
              bFilenameFound = kTRUE;
              break;
           }
         } // while( !optionFilenameFile.eof() )
         if( optionFilenameFile.eof() && kFALSE == bFilenameFound )
         {
            cout<<"************************************************************************"<<endl;
            cout<<"Field for Vftx step not found in File with option filename => Using "<<sOptionFileName<<endl;
         } // if( optionFilenameFile.eof() && kFALSE == bFilenameFound )
      } // else of if( optionFilenameFile.fail() == true)

   // Read the option file
   fstream setupFile(sOptionFileName, ios::in);
   
   // Testing if the option does exist. If not I use default values.
   if( setupFile.fail() == true)
   {
      cout<<"Error for TVftxParam: Setup file "<<sOptionFileName<<" can not be opened or is missing."<<endl;
      cout<<"=> Using default values!"<<endl;
   }
   else
   {
      TString line;
      
      // Goes through all lines
      while( !setupFile.eof() )
      {
         line.ReadLine(setupFile, kFALSE); // Read a line of the option file and set the iterator automatically to the next line
         if(1 == uDebug)
            cout<<line<<endl;

         if(line(0) == '#' || line(0) == '*')
         {
            //Comment in the text file
            ;
         }
         else if(line.Contains("debug")==kTRUE)
         {
            uDebug = ((TString)line(5,10)).Atoi();
            if(1 == uDebug)
               cout<<"Debug ON!!!!!!"<<endl;
         }
         else if(line.Contains("vftxcalena")==kTRUE)
         {
            line = line(11,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  uVftxCalHistosEnabled[temp_index] = ((TString)line(0,3)).Atoi();
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("refonechan")==kTRUE)
         {
            line = line(11,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  iVftxReference1Channel[temp_index] = ((TString)line(0,3)).Atoi();
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("reftwochan")==kTRUE)
         {
            line = line(11,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  iVftxReference2Channel[temp_index] = ((TString)line(0,3)).Atoi();
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("mainreftdc")==kTRUE)
         {
            iMainReferenceTdc = ((TString)line(11,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test iMainReferenceTdc: "<<iMainReferenceTdc<<endl;
         }
         else if(line.Contains("chcoimap")==kTRUE)
         {
            uVftxCoincidenceMap = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uVftxCoincidenceMap: "<<uVftxCoincidenceMap<<endl;
         }
         else if(line.Contains("bitcontrol")==kTRUE)
         {
            uBitControl = ((TString)line(10,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uBitControl: "<<uBitControl<<endl;
         }
         else if(line.Contains("coarsetimehisto")==kTRUE)
         {
            uCoarseTimeHisto = ((TString)line(15,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uCoarseTimeHisto: "<<uCoarseTimeHisto<<endl;
         }
         else if(line.Contains("finetime")==kTRUE)
         {
            uFineHistEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uFineHistEnable: "<<uFineHistEnable<<endl;
         }
         else if(line.Contains("finetevo")==kTRUE)
         {
            uFineEvolutionHistEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uFineEvolutionHistEnable: "<<uFineEvolutionHistEnable<<endl;
         }
         else if(line.Contains("calibena")==kTRUE)
         {
            uEnableCalib = ((TString)line(9,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uEnableCalib: "<<uEnableCalib<<endl;
         }
         else if(line.Contains("calibnb")==kTRUE)
         {
            iMinNbHitsCalib = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test iMinNbHitsCalib: "<<iMinNbHitsCalib<<endl;
         }
         else if(line.Contains("initialcalibfile")==kTRUE)
         {
            sInitialCalibrationFilename = (TString)line(17,128);
            if(1 == uDebug)
               cout<<"Test sInitialCalibrationFilename: "<<sInitialCalibrationFilename<<endl;
         } 
         else if(line.Contains("inicalindex")==kTRUE)
         {
            line = line(12,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  uVftxInitalCalIndex[temp_index] = ((TString)line(0,3)).Atoi();
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("caliboutena")==kTRUE)
         {
            uEnableCalibOutput = ((TString)line(12,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uEnableCalibOutput: "<<uEnableCalibOutput<<endl;
         }
         else if(line.Contains("timeplot")==kTRUE)
         {
            uTimeHistEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uTimeHistEnable: "<<uTimeHistEnable<<endl;
         }
         else if(line.Contains("timesing")==kTRUE)
         {
            uTimeHistSinglesEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uTimeHistSinglesEnable: "<<uTimeHistSinglesEnable<<endl;
         }
         else if(line.Contains("totplot")==kTRUE)
         {
            uTotHistoEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uTotHistoEnable: "<<uTotHistoEnable<<endl;
         }
         else if(line.Contains("muldist")==kTRUE)
         {
            uMultiHitsDistanceHistoEnable = ((TString)line(8,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uMultiHitsDistanceHistoEnable: "<<uMultiHitsDistanceHistoEnable<<endl;
         }
         else if(line.Contains("manuoffs")==kTRUE)
         {
            uManualTdcOffsetEnable = ((TString)line(8,10)).Atoi();
            if( 1 == uManualTdcOffsetEnable )
            {
               uAutomaticOffsetEnable = 0;
               uTdcOffsetEnable       = 1;
            }
            if(1 == uDebug)
               cout<<"Test uManualTdcOffsetEnable: "<<uManualTdcOffsetEnable<<endl;
         }
         else if(line.Contains("tdcoffsm")==kTRUE && 1 == uManualTdcOffsetEnable)
         {
            line = line(12,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  iAutomaticTdcOffset[temp_index] = ((TString)line(0,3)).Atoi();
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("autooffs")==kTRUE)
         {
            if( 0 == uManualTdcOffsetEnable )
            {
               uAutomaticOffsetEnable = ((TString)line(8,10)).Atoi();
               if( 1 == uAutomaticOffsetEnable )
                  uTdcOffsetEnable       = 1;
               if(1 == uDebug)
                  cout<<"Test uAutomaticOffsetEnable: "<<uAutomaticOffsetEnable<<endl;
            }
               else cout<<"Ignored uAutomaticOffsetEnable as uManualTdcOffsetEnable is ON"<<endl;
         }
         else if(line.Contains("coarsecorrt")==kTRUE)
         {
            uUseCoarseCorrectedTime = ((TString)line(12,10)).Atoi();
         }
         else if(line.Contains("singchcalib")==kTRUE)
         {
            uSingleChannelCalibFilesEnable = ((TString)line(11,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uSingleChannelCalibFilesEnable: "<<uSingleChannelCalibFilesEnable<<endl;
         }
         else if(line.Contains("schcalibout")==kTRUE)
         {
            uSingleChannelCalibFilesOutput = ((TString)line(11,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uSingleChannelCalibFilesOutput: "<<uSingleChannelCalibFilesOutput<<endl;
         }
         else if(line.Contains("tdcboard")==kTRUE)
         {
            line = line(12,3*MAX_FPGA_TDC);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
               {
                  iVftxBoardIndex[temp_index] = ((TString)line(0,3)).Atoi();
                  if( MAX_FPGA_TDC < iVftxBoardIndex[temp_index] )
                     iVftxBoardIndex[temp_index] = -1;
                  line = line(3,3*MAX_FPGA_TDC);
               } // for(UInt_t temp_index = 0; temp_index < MAX_FPGA_TDC && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("offcalib")==kTRUE)
         {
            uEnableTimeOffsetCalibration = ((TString)line(9,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uEnableTimeOffsetCalibration: "<<uEnableTimeOffsetCalibration<<endl;
         }
         else if(line.Contains("chanoffs")==kTRUE)
         {
            Int_t iTdc= ((TString)line(8,2)).Atoi();
            if( iTdc < MAX_FPGA_TDC )
            {
               line = line(10,6*FPGA_TDC_NBCHAN/2);
               if( 0 != line.Sizeof() )
               {
                  for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
                  {
                     dTimeOffset[iTdc][temp_index] = ((TString)line(0,6)).Atof();
                     line = line(6,6*FPGA_TDC_NBCHAN/2);
                  } // for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
               } // if( 0 != line.Sizeof() )
            } // if( iTdc < MAX_FPGA_TDC )
         }
         else if(line.Contains("chanalloff")==kTRUE)
         {
            line = line(10,6*FPGA_TDC_NBCHAN/2);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
               {
                  dMeanTimeOffset[temp_index] = ((TString)line(0,6)).Atof();
                  line = line(6,6*FPGA_TDC_NBCHAN/2);
               } // for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
         else if(line.Contains("totcalib")==kTRUE)
         {
            uEnableTotCalibration = ((TString)line(9,10)).Atoi();
            if(1 == uDebug)
               cout<<"Test uEnableTotCalibration: "<<uEnableTotCalibration<<endl;
         }
         else if(line.Contains("totoffs")==kTRUE)
         {
            Int_t iTdc= ((TString)line(7,2)).Atoi();
            if( iTdc < MAX_FPGA_TDC )
            {
               line = line(10,6*FPGA_TDC_NBCHAN/2);
               if( 0 != line.Sizeof() )
               {
                  for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
                  {
                     dTotOffset[iTdc][temp_index] = ((TString)line(0,6)).Atof();
                     line = line(6,6*FPGA_TDC_NBCHAN/2);
                  } // for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
               } // if( 0 != line.Sizeof() )
            } // if( iTdc < MAX_FPGA_TDC )
         }
         else if(line.Contains("totalloff")==kTRUE)
         {
            line = line(10,6*FPGA_TDC_NBCHAN/2);
            if( 0 != line.Sizeof() )
            {
               for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
               {
                  dMeanTotOffset[temp_index] = ((TString)line(0,6)).Atof();
                  line = line(6,6*FPGA_TDC_NBCHAN/2);
               } // for(UInt_t temp_index = 0; temp_index < FPGA_TDC_NBCHAN/2 && 0 != line.Sizeof(); temp_index++)
            } // if( 0 != line.Sizeof() )
         }
      } // while( !setupFile.eof() )
   } //  else of if( setupFile.fail() == true)
   if( uEnableCalib )
   {
      cout<<" Fine time Histos needed for corrections => Enable!!"<<endl;
      uFineHistEnable = 1;

      if( -1 == iMinNbHitsCalib &&
          ( kTRUE == sInitialCalibrationFilename.EqualTo("") ||
            kTRUE == sInitialCalibrationFilename.EqualTo("-") ) &&
           0 == uSingleChannelCalibFilesEnable )
      {
         cout<<" Nb of hits per channel needed for corrections disabled while calibration file disabled ";
         cout<<"=> Enable iMinNbHitsCalib and set it to 400!!"<<endl;
         iMinNbHitsCalib = 400;
      }
   }
   
   this->PrintOptions(); //print out all values to see, if the setting has worked correctly
   return kTRUE;
}


Int_t TVftxParam::PrintOptions(){
   cout<<"********************* VFTX calibration parameters **********************"<<endl;
   if(1 == uDebug)
      cout<<"Debug ON!!!!!!"<<endl;
      else cout<<"Debug OFF"<<endl;
   cout<<"VFTX FPGA TDC index:       |-      ";
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      cout.width(2);
      cout<<iIndexVftx<<" ";
   }
   cout<<endl<<"Calibration histo. enabled |->     ";
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      cout.width(2);
      cout<<uVftxCalHistosEnabled[iIndexVftx] <<" ";
   }
   cout<<endl<<"1st reference channel      |->     ";
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      cout.width(2);
      cout<<iVftxReference1Channel[iIndexVftx] <<" ";
   }
   cout<<endl<<"2nd reference channel      |->     ";
   for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
   {
      cout.width(2);
      cout<<iVftxReference2Channel[iIndexVftx] <<" ";
   }
   cout<<endl;
   if( -1 < iMainReferenceTdc )
      cout<<"Main reference tdc            :     "<<iMainReferenceTdc<<endl;
      else cout<<"Main reference tdc            :     OFF"<<endl;

   cout<<"Channel coincidence mapping   :     "<<uVftxCoincidenceMap<<endl;
   cout<<"Control bit Histograms        :     "<<uBitControl<<endl; 
   cout<<"Fine Time Histograms          :     "<<uFineHistEnable<<endl;
   cout<<"Fine Time Evolution Histograms:     "<<uFineEvolutionHistEnable<<endl;
   cout<<"Coarse time Histograms        :     "<<uCoarseTimeHisto<<endl;
   if(1 == uEnableCalib)
      cout<<"Calibration                   :     ON"<<endl;
      else cout<<"Calibration                   :     OFF"<<endl;
   if( -1 == iMinNbHitsCalib &&
         kTRUE != sInitialCalibrationFilename.EqualTo("") && kTRUE != sInitialCalibrationFilename.EqualTo("-") )
   {
      cout<<"Filename for calib hist:            "<<sInitialCalibrationFilename<<endl;
      cout<<"VFTX FPGA TDC index:       |-      ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<iIndexVftx<<" ";
      }
      cout<<endl<<"Tdc initial calib. index:  |->     ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<uVftxInitalCalIndex[iIndexVftx] <<" ";
      }
      cout<<endl;
   }
      else
      {
         cout<<"Min nb hits for calib         :     "<<iMinNbHitsCalib<<endl;
         if( kTRUE != sInitialCalibrationFilename.EqualTo("") && kTRUE != sInitialCalibrationFilename.EqualTo("-") )
         {
            cout<<"Filename for intial calib hist:     "<<sInitialCalibrationFilename<<endl;
            cout<<"VFTX FPGA TDC index:       |-      ";
            for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
            {
               cout.width(2);
               cout<<iIndexVftx<<" ";
            }
            cout<<endl<<"Tdc initial calib. index:  |->     ";
            for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
            {
               cout.width(2);
               cout<<uVftxInitalCalIndex[iIndexVftx] <<" ";
            }
            cout<<endl;
         }
      }
   if(1 == uEnableCalibOutput)
      cout<<"Calibration saved in root file:     ON"<<endl;
      else cout<<"Calibration saved in root file:     OFF"<<endl;
   if( 1 == uTimeHistEnable )
      cout<<"Time Histograms               :     ON"<<endl;
      else cout<<"Time Histograms               :     OFF"<<endl;
   if( 1 == uTimeHistSinglesEnable )
      cout<<"Time Histograms Multiplicity 1:     ON"<<endl;
      else cout<<"Time Histograms Multiplicity 1:     OFF"<<endl;
   if( 1 == uTotHistoEnable )
      cout<<"Tot  Histograms               :     ON"<<endl;
      else cout<<"Tot  Histograms               :     OFF"<<endl;
   if( 1 == uMultiHitsDistanceHistoEnable )
      cout<<"Histograms Distance Multi Hits:     ON"<<endl;
      else cout<<"Histograms Distance Multi Hits:     OFF"<<endl;
   if(1 == uManualTdcOffsetEnable)
   {
      cout<<"Manual tdc offset detection:        ON"<<endl;
      cout<<"VFTX FPGA TDC index:       |-      ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<iIndexVftx<<" ";
      }
      cout<<endl<<"Manual offset val., clock: |->     ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<iAutomaticTdcOffset[iIndexVftx] <<" ";
      }
      cout<<endl;
   }
      else cout<<"Manual tdc offset detection:        OFF"<<endl;
   if(1 == uAutomaticOffsetEnable)
      cout<<"Automatic tdc offset detection:     ON"<<endl;
      else cout<<"Automatic tdc offset detection:     OFF"<<endl;
   if( 1 == uUseCoarseCorrectedTime )
      cout<<"Coarse time cycle correc.:          ON"<<endl;
      else cout<<"Coarse time cycle correc.:          OFF"<<endl;
   if(1 == uSingleChannelCalibFilesEnable)
      cout<<"Use single channel calib files:     ON"<<endl;
      else cout<<"Use single channel calib files:     OFF"<<endl;
   switch( uSingleChannelCalibFilesOutput )
   {
      case 0:
         cout<<"Single channel calib files output:  OFF"<<endl;
         break;
      case 1:
         cout<<"Single channel calib files output:  New files from data"<<endl;
         break;
      case 2:
         cout<<"Single channel calib files output:  Update files with data"<<endl;
         break;
      default:
         break;
   }
   if( 1 == uEnableTimeOffsetCalibration ||
       1 == uEnableTotCalibration )
   {
      cout<<"VFTX FPGA TDC slot index:  |-      ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<iIndexVftx<<" ";
      }
      cout<<endl<<"VFTX FPGA TDC board index: |->     ";
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
      {
         cout.width(2);
         cout<<iVftxBoardIndex[iIndexVftx] <<" ";
      }
      cout<<endl;
   }
   if( 1 == uEnableTimeOffsetCalibration )
   {
      cout<<"Time offset calibration:            ON"<<endl;
      cout<<"Channel:                       |-  ";
      for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
      {
         cout.width(5);
         cout<<iIndexChannel<<" ";
      }
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
         if( 1 == uVftxCalHistosEnabled[iIndexVftx] )
         {
            if( -1 < iVftxBoardIndex[iIndexVftx] )
            {
               cout<<endl<<Form("Slot %02d Board #%02d Time offset: |-> ", iIndexVftx, iVftxBoardIndex[iIndexVftx]);
               for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
               {
                  cout.width(5);
                  cout<<dTimeOffset[ iVftxBoardIndex[iIndexVftx] ][iIndexChannel] <<" ";
               }
            } // if( -1 < iVftxBoardIndex[iIndexVftx] )
               else
               {
                  cout<<endl<<Form("Slot %02d def. mean Time offset: |-> ", iIndexVftx );
                  for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
                  {
                     cout.width(5);
                     cout<<dMeanTimeOffset[iIndexChannel] <<" ";
                  }
               } // else of if( -1 < iVftxBoardIndex[iIndexVftx] )
         } // if( 1 == uVftxCalHistosEnabled[iIndexVftx] )
      cout<<endl;
   } // if( 1 == uEnableTimeOffsetCalibration )
      else cout<<"Time offset calibration:            OFF"<<endl;
   if( 1 == uEnableTotCalibration)
   {
      cout<<"Tot offset calibration:             ON"<<endl;
      cout<<"Channel:                       |-  ";
      for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
      {
         cout.width(5);
         cout<<iIndexChannel<<" ";
      }
      for( Int_t iIndexVftx = 0; iIndexVftx < MAX_FPGA_TDC; iIndexVftx++)
         if( 1 == uVftxCalHistosEnabled[iIndexVftx] )
         {
            if( -1 < iVftxBoardIndex[iIndexVftx] )
            {
               cout<<endl<<Form("Slot %02d Board #%02d Tot offset:  |-> ", iIndexVftx, iVftxBoardIndex[iIndexVftx]);
               for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
               {
                  cout.width(5);
                  cout<<dTotOffset[ iVftxBoardIndex[iIndexVftx] ][iIndexChannel] <<" ";
               }
            } // if( -1 < iVftxBoardIndex[iIndexVftx] )
               else
               {
                  cout<<endl<<Form("Slot %02d def. mean Tot offset:  |-> ", iIndexVftx );
                  for( Int_t iIndexChannel = 0; iIndexChannel < FPGA_TDC_NBCHAN/2; iIndexChannel++)
                  {
                     cout.width(5);
                     cout<<dMeanTotOffset[iIndexChannel] <<" ";
                  }
               } // else of if( -1 < iVftxBoardIndex[iIndexVftx] )
         } // if( 1 == uVftxCalHistosEnabled[iIndexVftx] )
      cout<<endl;
   } // if( 1 == uEnableTotCalibration)
      else cout<<"Tot offset calibration:             OFF"<<endl;

   cout<<"************************************************************************"<<endl;
   
   return 0;
}