ROCsoft: beamtime/tof-tdctest/go4/VFTX/TVftxProc.cxx (r4864/r4860) Source File

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00001 #include "TVftxProc.h"
00002 #include "MBSUNPACK/TMbsCrateProc.h"
00003 
00004 #include "TTimeStamp.h"
00005 
00006 TVftxProc::TVftxProc(const char* name) : TCBMBeamtimeProc(name),fCrateInputEvent(0), fOutputEvent(0),fTriglogInputEvent(0)
00007 {
00008    TGo4Log::Info("**** TVftxProc: Create instance %s" , name );
00009 
00010    fPar = (TVftxParam*) MakeParameter("VftxPar", "TVftxParam");
00011    fParAnalysis = (TGsiAug12Param*) GetParameter("GsiAug12Par");
00012 
00013    //~ cout<<name<<endl;
00014    iFirstModuleWithReference2   = -1;
00015    iFirstModuleWithReference1 = -1;
00016 
00017    // If the main reference tdc is defined, try to use its reference channels
00018    if( -1 < fPar->iMainReferenceTdc)
00019    {
00020       if( -1 < fPar->iVftxReference1Channel[fPar->iMainReferenceTdc])
00021          iFirstModuleWithReference1 = fPar->iMainReferenceTdc;
00022       if( -1 < fPar->iVftxReference2Channel[fPar->iMainReferenceTdc])
00023          iFirstModuleWithReference2 = fPar->iMainReferenceTdc;
00024    } // if( -1 < fPar->iMainReferenceTdc)
00025 
00026    for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00027    { 
00028       if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00029       {
00030          fEventSizeHeader1[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader1_%d",imodule,imodule),
00031                      "Size of the event in event header", 256, -0.5, 255.5,"Size [words]");
00032          fEventSizeHeader2[imodule] = MakeTH1('I', Form("FPGA/tdc%d/EvtSizeHeader2_%d",imodule,imodule),
00033                      "Size of the event in tdc header", 256, -0.5, 255.5,"Size [words]");
00034          fTriggerType[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerType%d",imodule,imodule),
00035                      "Trigger type in tdc header", 4, -0.5, 3.5,"Type []");
00036          fTriggerTime[imodule] = MakeTH1('I', Form("FPGA/tdc%d/TriggerTime%d",imodule,imodule),
00037                      "Time of the trigger in the coarse counter", 16383, 0, 16383,"Bin []");
00038                
00039          fChanUsage[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanUsage%d",imodule,imodule),
00040                    "Data on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00041          fChanEvents[imodule] = MakeTH1('I', Form("FPGA/ChanEvents%d",imodule),
00042                     "Data on channel during this event?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Events []");
00043                
00044          fChanFuture[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanFuture%d",imodule,imodule),
00045                     "Channel in future?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00046            
00047          fChanDouble[imodule] = MakeTH1('I', Form("FPGA/tdc%d/ChanDouble%d",imodule,imodule),
00048                     "Double on channel?", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,"Channel []","Counts []");
00049            
00050          fChanMultip[imodule] = MakeTH2('I', Form("FPGA/tdc%d/fChanMultip%d",imodule,imodule),
00051                     "Multiplicity per channel", FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00052                     TVftxBoardData::MaxMult+1, 0, TVftxBoardData::MaxMult+1, "Channel []","Multiplicity []","Counts []");
00053 
00054          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00055          {
00056             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistEnable )
00057                fTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/time/chan%02dTime%d",imodule,ichan,imodule),
00058                       Form("Time to trigger Tdc %d channel %2d",imodule, ichan),
00059                       8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00060 
00061             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTimeHistSinglesEnable )
00062                fTimeSingles[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/timeSingles/chan%02dTimeSingles%d",imodule,ichan,imodule),
00063                       Form("Time to trigger Tdc %d channel %2d for events with only one hit",imodule, ichan),
00064                       8000, -700000, 100000, "Trigger time - Calibrated Time [ps]");
00065 
00066             if( 1 == fPar->uMultiHitsDistanceHistoEnable)
00067             {
00068                fMultihitsDistance[imodule][ichan]
00069                      = MakeTH2('I', Form("FPGA/tdc%d/multiDist/chan%02dMultiDist%d",imodule,ichan,imodule),
00070                               Form("Time to previous hit for multiple hits Tdc %d channel %2d",imodule, ichan),
00071                               7500, -50000, 100000,
00072                               TVftxBoardData::MaxMult, 1, TVftxBoardData::MaxMult + 1,
00073                               "T(n) - T(n-1) [ps]",
00074                               "n (Multiple hits index) []");
00075                fSecondHitDistance[imodule][ichan]
00076                      = MakeTH2('I', Form("FPGA/tdc%d/SecDist/chan%02dSecDist%d",imodule,ichan,imodule),
00077                               Form("Time to 1st hit for second hits Tdc %d channel %2d",imodule, ichan),
00078                               1000, -500, 500,
00079                               50, -15, 35,
00080                               "FT(2) - FT(1) [bins]",
00081                               "Coarse(2) - Coarse(1) [Clock Cycle]");
00082             }
00083 
00084             if( 1 == fPar->uFineHistEnable )
00085             {
00086                TString sHistoName = Form("chan%02dFineTime%d",ichan,imodule);
00087                TString sHistoFullPath = Form("FPGA/tdc%d/ft/%s",imodule, sHistoName.Data() );
00088                TString sHistoTitle = Form("FineTime Tdc %d channel %2d",imodule, ichan);
00089                fFineTime[imodule][ichan] = MakeTH1('I', sHistoFullPath,
00090                      sHistoTitle,
00091                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00092                      "Fine Time [bin]");
00093                fFineTime[imodule][ichan]->Reset();
00094                TGo4Analysis::Instance()->ProtectObjects( sHistoName, "+C");
00095             }
00096 
00097             iNbHitsForCalib[imodule][ichan] = 0;
00098             for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00099                dCorr[imodule][ichan][ibin] = 0;
00100          }
00101          if( 1 == fPar->uFineEvolutionHistEnable )
00102             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00103             {
00104                fFineTimeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%02dFineTimeEvo%d",imodule,ichan,imodule),
00105                      Form("FineTime Tdc %d channel %2d",imodule, ichan),
00106                      72, -0.5, 72 - 0.5,
00107                      TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00108                      "Time [h]", "Fine Time [bin]");
00109                fBinSizeEvo[imodule][ichan] = MakeTH2('I', Form("FPGA/tdc%d/ft_evo/chan%02dBinSizeEvo%d",imodule,ichan,imodule),
00110                      Form("Bin Size Tdc %d channel %2d",imodule, ichan),
00111                      200, -0.5, 1000- 0.5,
00112                      50, -0.5, 50 - 0.5,
00113                      "Time [min]", "Bin Size [ps]");
00114             }
00115       
00116       //histograms for the non-linear correction
00117          if( 1 == fPar->uEnableCalib )
00118          {
00119             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00120             {
00121                fDnlCh[imodule][ichan] = MakeTH1('D', Form("FPGA/tdc%d/DnlCh/chan%02dDnlCh%d",imodule,ichan,imodule),
00122                          Form("Dnl per bin Tdc %d channel %2d",imodule, ichan),
00123                          TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00124                          "Fine Time [bin]");
00125                fDnlCorr[imodule][ichan] = MakeTH1('D', Form("FPGA/tdc%d/Dnl/chan%02dDnlCorr%d",imodule,ichan,imodule),
00126                          Form("DnlSum Tdc %d channel %2d",imodule, ichan),
00127                          TDC_FIFO_FINE_CT, -0.5, TDC_FIFO_FINE_CT - 0.5,
00128                          "Fine Time [bin]");
00129             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00130 
00131             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uTotHistoEnable )
00132                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN/2; ichan++)
00133                {
00134                   fToT[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/tot/chan%02dToT%d",imodule,ichan,imodule),
00135                     Form("ToT Tdc %d channel %2d",imodule, ichan),
00136                     30000, -150000, 150000, "ToT [ps]");
00137 
00138                   // Test
00139                   /*
00140                   fHitMergingTest[imodule][ichan]
00141                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest%d",imodule,ichan,imodule),
00142                                Form("Leading time 2nd hit - leading time 1st hit vs tot 1st hit Tdc %d channel %2d",imodule, ichan),
00143                                200, -5000, 35000,
00144                                200, -5000, 35000,
00145                                "Tot(0) = Trailing(0) - Leading(0) [ps]",
00146                                "Leading(1) - Leading(0) [ps]");
00147                   fHitMergingTest2[imodule][ichan]
00148                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest2_%d",imodule,ichan,imodule),
00149                                 Form("Leading Time 2nd hit - trailing time 1st hit vs tot 1st hit Tdc %d channel %2d",imodule, ichan),
00150                                 200, -5000, 35000,
00151                                 250, -25000, 25000,
00152                                 "Tot(0) = Trailing(0) - Leading(0) [ps]",
00153                                 "Leading(1) - Trailing(0) [ps]");
00154                   fHitMergingTest3[imodule][ichan]
00155                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest3_%d",imodule,ichan,imodule),
00156                                 Form("Trailing time 2nd hit - trailing time 1st hit vs tot 1st hit Tdc %d channel %2d",imodule, ichan),
00157                                 200, -5000, 35000,
00158                                 200, -5000, 35000,
00159                                 "Tot(0) = Trailing(0) - Leading(0) [ps]",
00160                                 "Trailing(1) - Trailing(0) [ps]");
00161                   fHitMergingTest4[imodule][ichan]
00162                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest4_%d",imodule,ichan,imodule),
00163                                 Form("Trailing time diff vs Leading Time diff, 1st/2nd hit, Tdc %d channel %2d",imodule, ichan),
00164                                 200, -5000, 35000,
00165                                 200, -5000, 35000,
00166                                 "Leading(1) - Leading(0) [ps]",
00167                                 "Trailing(1) - Trailing(0) [ps]");
00168                   fHitMergingTest5[imodule][ichan]
00169                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest5_%d",imodule,ichan,imodule),
00170                                 Form("Tot 2nd hit vs tot 1st hit Tdc %d channel %2d",imodule, ichan),
00171                                 200, -5000, 35000,
00172                                 200, -5000, 35000,
00173                                 "Tot(0) = Trailing(0) - Leading(0) [ps]",
00174                                 "Tot(1) = Trailing(1) - Leading(1) [ps]");
00175                   fHitMergingTest6[imodule][ichan]
00176                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest6_%d",imodule,ichan,imodule),
00177                                 Form("FT 2nd hit leading time vs FT 1st hit leading time Tdc %d channel %2d",imodule, ichan),
00178                                 500, 0, 500,
00179                                 500, 0, 500,
00180                                 "FT_Leading(0) []",
00181                                 "FT_Leading(1) []");
00182                   fHitMergingTest7[imodule][ichan]
00183                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest7_%d",imodule,ichan,imodule),
00184                                 Form("FT 2nd hit trailing time vs FT 1st hit trailing time Tdc %d channel %2d",imodule, ichan),
00185                                 500, 0, 500,
00186                                 500, 0, 500,
00187                                 "FT_Trailing(0) []",
00188                                 "FT_Trailing(1) []");
00189                   fHitMergingTest8[imodule][ichan]
00190                       = MakeTH2('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest9_%d",imodule,ichan,imodule),
00191                                 Form("Multiplicity trailing vs multiplicity leading Tdc %d channel %2d",imodule, ichan),
00192                                 TVftxBoardData::MaxMult, 0, TVftxBoardData::MaxMult,
00193                                 TVftxBoardData::MaxMult, 0, TVftxBoardData::MaxMult,
00194                                 "Mult Rising []",
00195                                 "Mult Falling []");
00196 
00197                   fHitMergingTest14[imodule][ichan]
00198                       = MakeTH1('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest14_%d",imodule,ichan,imodule),
00199                                 Form("CT 2nd hit leading time - CT 1st hit leading time Tdc %d channel %2d",imodule, ichan),
00200                                 200, -100, 100,
00201                                 "CT_Leading(1) - CT_Leading(0) []");
00202                   fHitMergingTest15[imodule][ichan]
00203                       = MakeTH1('I', Form("FPGA/tdc%d/Test/chan%02dfHitMergingTest15_%d",imodule,ichan,imodule),
00204                                 Form("CT 2nd hit trailing time - CT 1st hit trailing time Tdc %d channel %2d",imodule, ichan),
00205                                 200, -100, 100,
00206                                 "CT_Trailing(1) - CT_Trailing(0) []");
00207 
00208                   if( 6 == imodule && 16 == ichan)
00209                   {
00210                      for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++)
00211                      {
00212                         fHitMergingTest9[imul]
00213                             = MakeTH1('I', Form("FPGA/tdc%d/Test/Tot/chan%02dfHitMergingTest9_%d_%d",imodule,ichan,imodule, imul),
00214                                       Form("Tot multiple hit %d Tdc %d channel %2d", imul,imodule, ichan),
00215                                       250, -25000, 25000,
00216                                       Form("Tot = Trailing - Leading Edge(%d) [ps]", imul));
00217                         fHitMergingTest10[0][imul]
00218                             = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/Lchan%02dfHitMergingTest10_%d_%d",imodule,ichan,imodule, imul),
00219                                   Form("Time to trigger multiple hit %d Tdc %d channel %2d", imul,imodule, ichan),
00220                                   1250, -400000, 100000,
00221                                   Form("Trigger time - Calibrated Time Edge(%d) [ps]", imul));
00222                         fHitMergingTest10[1][imul]
00223                             = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/Tchan%02dfHitMergingTest10_%d_%d",imodule,ichan,imodule, imul),
00224                                   Form("Time to trigger multiple hit %d Tdc %d channel %2d", imul,imodule, ichan),
00225                                   1250, -400000, 100000,
00226                                   Form("Trigger time - Calibrated Time Edge(%d) [ps]", imul));
00227                      } // for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++)
00228                      fHitMergingTest11[0]
00229                          = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/chan%02dfHitMergingTest11_%d_%d",imodule,ichan,imodule, 0),
00230                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 0,imodule, ichan),
00231                                1250, -400000, 100000,
00232                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 0));
00233                      fHitMergingTest11[1]
00234                          = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/chan%02dfHitMergingTest11_%d_%d",imodule,ichan,imodule, 1),
00235                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 1,imodule, ichan),
00236                                1250, -400000, 100000,
00237                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 1));
00238                      fHitMergingTest11[2]
00239                          = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/chan%02dfHitMergingTest11_%d_%d",imodule,ichan,imodule, 2),
00240                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 2,imodule, ichan),
00241                                1250, -400000, 100000,
00242                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 2));
00243                      fHitMergingTest11[3]
00244                          = MakeTH1('I', Form("FPGA/tdc%d/Test/Time/chan%02dfHitMergingTest11_%d_%d",imodule,ichan,imodule, 3),
00245                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 3,imodule, ichan),
00246                                1250, -400000, 100000,
00247                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 3));
00248 
00249                      fHitMergingTest12[0]
00250                          = MakeTH1('I', Form("FPGA/tdc%d/Test/2Time/chan%02dfHitMergingTest12_%d_%d",imodule,ichan,imodule, 0),
00251                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 0,imodule, ichan),
00252                                1250, -400000, 100000,
00253                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 0));
00254                      fHitMergingTest12[1]
00255                          = MakeTH1('I', Form("FPGA/tdc%d/Test/2Time/chan%02dfHitMergingTest12_%d_%d",imodule,ichan,imodule, 1),
00256                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 1,imodule, ichan),
00257                                1250, -400000, 100000,
00258                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 1));
00259 
00260                      fHitMergingTest13[0]
00261                          = MakeTH2('I', Form("FPGA/tdc%d/Test/2Time/chan%02dfHitMergingTest13_%d_%d",imodule,ichan,imodule, 0),
00262                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 0,imodule, ichan),
00263                                300, -300000, 0,
00264                                300, -300000, 0,
00265                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 0),
00266                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 1));
00267 
00268                      fHitMergingTest13[1]
00269                          = MakeTH2('I', Form("FPGA/tdc%d/Test/2Time/chan%02dfHitMergingTest13_%d_%d",imodule,ichan,imodule, 1),
00270                                Form("Time to trigger multiple hit %d Tdc %d channel %2d", 1,imodule, ichan),
00271                                300, -300000, 0,
00272                                300, -300000, 0,
00273                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 0),
00274                                Form("Trigger time - Calibrated Time Edge(%d) [ps]", 1));
00275                   } // if( 6 == imodule && 16 == ichan)
00276                   */
00277                } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN/2; ichan++)
00278          } // if( 1 == fPar->uEnableCalib )
00279       
00280          if( 1 == fPar->uBitControl)
00281          {
00282             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00283             {
00284                bitcontrol[imodule][ichan] = MakeTH1('I',
00285                          Form("FPGA/tdc%d/bits%d/chan%02dBitcontrol%d",imodule,imodule,ichan,imodule),
00286                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00287                          TDC_FIFO_COARSE_CT_SHIFT, 0, TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00288                bitcontrolCoarse[imodule][ichan] = MakeTH1('I',
00289                          Form("FPGA/tdc%d/bits%dCoarse/chan%02dBitcontrol%dCoarse",imodule,imodule,ichan,imodule),
00290                          Form("use of bits Tdc %d channel %2d",imodule, ichan),
00291                          TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,
00292                          0, TDC_FIFO_FUTURE_BIT_SHIFT-TDC_FIFO_COARSE_CT_SHIFT,"Bit []");
00293             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00294          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl)
00295       
00296          if( 1 == fPar->uCoarseTimeHisto )
00297          {
00298             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00299             {
00300                fCoarseTime[imodule][ichan] = MakeTH1('I', Form("FPGA/tdc%d/ct/chan%02dCoarseTime%d",imodule,ichan,imodule),
00301                        Form("CoarseTime Tdc %d channel %2d",imodule, ichan),
00302                        TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT, -0.5, (TDC_FIFO_COARSE_CT >> TDC_FIFO_COARSE_CT_SHIFT)-0.5,
00303                        "Coarse Time [bin]");
00304             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00305          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00306 
00307          // Checking how diamond time relatice to trigger depend on the triggers
00308          if( -1 < fPar->iVftxReference2Channel[imodule] )
00309             fRef2TimeTriggerDep[imodule] = MakeTH2('I', Form("FPGA/tdc%d/Ref2VsTrigger%d",imodule,imodule),
00310                   Form("2nd reference (Diamond) Time to trigger depending on the active trigger, Tdc %d",imodule),
00311                   800, -395000, 5000, 16, 0, 16,
00312                   "Trigger time - 2nd reference (Diamond) Calibrated Time [ps]", "Trigger []");
00313 
00314          // If the main reference tdc is not defined or its 1st reference channel is invalid
00315          // Find first board with a 1st reference channel and then use it to compare the other boards
00316          // else compare main reference tdc to the other boards
00317          if( ( -1 == iFirstModuleWithReference1 || imodule == fPar->iMainReferenceTdc ) &&
00318                -1 < fPar->iVftxReference1Channel[imodule])
00319             iFirstModuleWithReference1 = imodule;
00320          else if( -1 < fPar->iVftxReference1Channel[imodule])
00321             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] &&
00322                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00323                fTdcResolutionRef1Check[imodule] = MakeTH1('I', Form("FPGA/Ref1Tdc%dVsTdc%d",imodule, iFirstModuleWithReference1 ),
00324                      Form("Time 1st reference signal Tdc %d against Tdc %d",imodule, iFirstModuleWithReference1),
00325                      30000, -15000, 15000,
00326                      Form("tRef1_%d - tRef1_%d [ps]", imodule, iFirstModuleWithReference1));
00327 
00328          // If the main reference tdc is not defined or its 2nd reference channel is invalid
00329          // Find first board with a 2nd reference channel and then use it to compare the other boards
00330          // else compare main reference tdc to the other boards
00331          if( ( -1 == iFirstModuleWithReference2 || imodule == fPar->iMainReferenceTdc ) &&
00332                -1 < fPar->iVftxReference2Channel[imodule])
00333             iFirstModuleWithReference2 = imodule;
00334          else if( -1 < fPar->iVftxReference2Channel[imodule] && -1 < iFirstModuleWithReference2)
00335             if( 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] &&
00336                 1 == fPar->uVftxCalHistosEnabled[imodule] )
00337                fTdcResolutionRef2Check[imodule] = MakeTH1('I', Form("FPGA/Ref2Tdc%dVsTdc%d",imodule, iFirstModuleWithReference2 ),
00338                      Form("Time 2nd reference (Diamond) signal Tdc %d against Tdc %d",imodule, iFirstModuleWithReference2),
00339                      30000, -15000, 15000,
00340                      Form("tref2_%d - tref2_%d [ps]", imodule, iFirstModuleWithReference2));
00341       } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00342    } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00343    uInitialMbsTime   = 0;
00344    uInitialVulomSync = 0;
00345 
00346    if( 1 == fPar->uVftxCoincidenceMap )
00347    {
00348       iMapIndex = 0;
00349       for( Int_t iModule1 = 0; iModule1 < MAX_FPGA_TDC; iModule1 ++)
00350          if( 1 == fPar->uVftxCalHistosEnabled[iModule1] )
00351          {
00352             for( Int_t iModule2 = iModule1; iModule2 < MAX_FPGA_TDC; iModule2 ++)
00353             {
00354                if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
00355                {
00356                   TGo4Log::Info("****Vftx monitor: Error creating mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
00357                         iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule1, iModule2);
00358                   break;
00359                }
00360                if( 1 == fPar->uVftxCalHistosEnabled[iModule2] )
00361                   fTdcChanStripMapping[ iMapIndex ] =
00362                            MakeTH2('I', Form("FPGA/Mapping/Mapp%d_%dVftx", iModule1, iModule2 ),
00363                                         Form("Channel during same event?, Tdc %d VS Tdc %d", iModule1, iModule2),
00364                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00365                                          FPGA_TDC_NBCHAN, -0.5, FPGA_TDC_NBCHAN - 0.5,
00366                                          Form("Channel Tdc #%d []", iModule1),
00367                                          Form("Channel Tdc #%d []", iModule2),"Events []");
00368                iMapIndex++;
00369             }
00370          }
00371          else iMapIndex += MAX_FPGA_TDC - iModule1; // To keep full array index
00372    } // if( 1 == fPar->uVftxCoincidenceMap )
00373 
00374    if( 1 == fPar->uEnableCalib )
00375    {
00376       if( 1 == fPar->uSingleChannelCalibFilesEnable )
00377       {
00378          TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00379          TGo4Log::Info("%s", sInfoLoading.Data() );
00380          sInfoLoading = "         ";
00381          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00382             sInfoLoading += Form("%2d ", ichan);
00383          TGo4Log::Info("%s", sInfoLoading.Data() );
00384 
00385          //define correction variables
00386          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00387          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00388 
00389          oldDir = gDirectory;
00390 
00391          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00392          {
00393             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00394                continue;
00395 
00396             sInfoLoading = Form("tdc #%2d: ",imodule );
00397             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00398             {
00399                TString sInitialCalibFileName = Form("./Calib/Tdc%02dChan%02d.root ", fPar->uVftxInitalCalIndex[imodule], ichan);
00400                TString sInitalCalibHistoName = "";
00401                fileCalibrationIn = new TFile( sInitialCalibFileName, "READ");
00402                if( kTRUE == fileCalibrationIn->IsOpen() )
00403                {
00404                   TH1* fInitialCalibHistoFromFile = 0;
00405                   sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00406                   fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHistoFromFile);
00407 
00408                   if( 0 == fInitialCalibHistoFromFile )
00409                      sInfoLoading += " 0 ";
00410                      else
00411                      {
00412                         sInfoLoading += " 1 ";
00413                         fInitialCalibHisto[imodule][ichan] = 0;
00414                         fInitialCalibHisto[imodule][ichan] = (TH1*)fInitialCalibHistoFromFile->Clone(Form("CalibSingleChanFile_tdc%02d_chan%02d", imodule, ichan));
00415                         fInitialCalibHisto[imodule][ichan]->SetDirectory( oldDir );
00416                         if( 0 != fInitialCalibHisto[imodule][ichan])
00417                         {
00418                            // Try to use initial calibration histo always
00419                            fDnlCh[imodule][ichan]->Reset();
00420                            fDnlCorr[imodule][ichan]->Reset();
00421                            //set a the sum to zero before summing over all bins in one channel
00422                            iSum[imodule][ichan] = 0;
00423                            Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00424 
00425                            for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00426                            {
00427                               Int_t iBinContent = (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00428                               //Looking for the used bins
00429                               if( iBinContent <= 0)
00430                               {
00431                                  bincontrol[ibin] = kFALSE;
00432                               }
00433                               else if( iBinContent > 0)
00434                               {
00435                                  bincontrol[ibin] = kTRUE;
00436                               }
00437 
00438                               // build the sum of all bin content
00439                               if(bincontrol[ibin])
00440                               {
00441                       iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00442                       dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00443                               }
00444                               else
00445                               {
00446                                  if( 0 < ibin)
00447                                     dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00448                                     else dCorr[imodule][ichan][ibin]=0;
00449                               }
00450                               fDnlCh[imodule][ichan]->Fill(ibin, (Double_t)iBinContent/dTotalEntriesInHisto );
00451                               fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00452                            } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00453                         } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00454                      } // else of if( 0 == fInitialCalibHistoFromFile )
00455                   fileCalibrationIn->Close();
00456                } // if( kTRUE == fileCalibrationIn->IsOpen() )
00457                   else sInfoLoading += " 0 ";
00458             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00459             TGo4Log::Info("%s", sInfoLoading.Data() );
00460          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00461       } // if( 1 == uSingleChannelCalibFilesEnable )
00462       else if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00463            kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") )
00464       {
00465          // Save online ROOT directory as the File opening auto change current Dir
00466          oldDir = gDirectory;
00467 
00468          TString sInitalCalibHistoName = "";
00469          fileCalibrationIn = new TFile( fPar->sInitialCalibrationFilename, "READ");
00470 
00471          if( kTRUE == fileCalibrationIn->IsOpen() )
00472          {
00473             TString sInfoLoading = "Loaded initial calibration histograms for following VFTX channels:";
00474             TGo4Log::Info("%s", sInfoLoading.Data() );
00475             sInfoLoading = "         ";
00476             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00477                sInfoLoading += Form("%2d ", ichan);
00478             TGo4Log::Info("%s", sInfoLoading.Data() );
00479 
00480             //define correction variables
00481             Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00482             Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00483 
00484             // Temp variable to store pointer on calib histo in File
00485             TH1* fInitialCalibHistoFromFile = 0;
00486 
00487             for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00488             {
00489                if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00490                   continue;
00491 
00492                sInfoLoading = Form("tdc #%2d: ",imodule );
00493                for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00494                {
00495                   fInitialCalibHistoFromFile = 0;
00496                   fInitialCalibHisto[imodule][ichan] = 0;
00497 
00498                   // Find histogram in file and store its pointer in a temp variable
00499                   sInitalCalibHistoName = Form("CalibHisto_tdc%02d_chan%02d", fPar->uVftxInitalCalIndex[imodule], ichan);
00500                   fileCalibrationIn->GetObject( sInitalCalibHistoName, fInitialCalibHistoFromFile);
00501 
00502                   if( 0 == fInitialCalibHistoFromFile )
00503                      sInfoLoading += " 0 ";
00504                      else
00505                      {
00506                         sInfoLoading += " 1 ";
00507                         // Clone the found histo and move it to online ROOT directory instead of File
00508                         fInitialCalibHisto[imodule][ichan] = (TH1*)fInitialCalibHistoFromFile->Clone(Form("CalibHistoFile_tdc%02d_chan%02d", imodule, ichan));
00509                         fInitialCalibHisto[imodule][ichan]->SetDirectory( oldDir );
00510                      }
00511 
00512                   if( 0 != fInitialCalibHisto[imodule][ichan])
00513                   {
00514                      // Try to use initial calibration histo always
00515                      fDnlCh[imodule][ichan]->Reset();
00516                      fDnlCorr[imodule][ichan]->Reset();
00517                      //set a the sum to zero before summing over all bins in one channel
00518                      iSum[imodule][ichan] = 0;
00519                      Double_t dTotalEntriesInHisto = (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00520 
00521                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00522                      {
00523                         Int_t iBinContent = (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00524                         //Looking for the used bins
00525                         if( iBinContent <= 0)
00526                         {
00527                            bincontrol[ibin] = kFALSE;
00528                         }
00529                         else if( iBinContent > 0)
00530                         {
00531                            bincontrol[ibin] = kTRUE;
00532                         }
00533 
00534                         // build the sum of all bin content
00535                         if(bincontrol[ibin])
00536                         {
00537                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00538                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00539                         }else
00540                         {
00541                            if( 0 < ibin)
00542                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00543                               else dCorr[imodule][ichan][ibin]=0;
00544                         }
00545                         fDnlCh[imodule][ichan]->Fill(ibin, (Double_t)iBinContent/dTotalEntriesInHisto );
00546                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );
00547                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00548                   } // if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00549                } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00550                TGo4Log::Info("%s", sInfoLoading.Data() );
00551             } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00552             // File closing and going back to online ROOT folder
00553             fileCalibrationIn->Close();
00554             gDirectory->Cd(oldDir->GetPath());
00555          } // if( kTRUE == fileCalibrationIn->IsOpen() )
00556             else
00557             {
00558                TGo4Log::Info("Could not open %s to load initial VFTX calibration, please check setting in Vftx_options.txt",
00559                                fPar->sInitialCalibrationFilename.Data() );
00560                for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00561                   for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00562                      fInitialCalibHisto[imodule][ichan] = 0;
00563             } // else of if( kTRUE == fileCalibrationIn->IsOpen() )
00564       } // if(  sInitialCalibrationFilename OK and 1 == fPar->uEnableCalib)
00565    } // if( 1 == fPar->uEnableCalib )
00566 
00567    //~ TGo4Log::Info("**** TVftxProc: Instance %s created", name );
00568 }
00569 
00570 
00571 TVftxProc::~TVftxProc()
00572 {
00573    cout << "**** TVftxProc: Delete instance " << endl;
00574    
00575    if(  kTRUE != fPar->sInitialCalibrationFilename.EqualTo("") &&
00576         kTRUE != fPar->sInitialCalibrationFilename.EqualTo("-") && 
00577         1 == fPar->uEnableCalib &&
00578         kTRUE == fileCalibrationIn->IsOpen() )
00579       fileCalibrationIn->Close();
00580       
00581    if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00582    {
00583       TTimeStamp timeCurrent;
00584       oldDir = gDirectory;
00585       TString sCalibOutFilename = Form("./VftxCalibHistos_%u_%u.root", timeCurrent.GetDate( kFALSE), timeCurrent.GetTime( kFALSE) );
00586       TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE", 
00587                                             Form("Calibration Data for VFTX, saved from analysis on %s", timeCurrent.AsString("lc") ), 
00588                                             9);
00589       if( kTRUE == fileCalibrationOut->IsOpen() )
00590       {
00591          sCalibOutFilename += ":/";
00592          gDirectory->Cd(sCalibOutFilename);
00593          TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00594          TGo4Log::Info("%s", sInfoSaving.Data() );
00595          sInfoSaving = "         ";
00596          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00597             sInfoSaving += Form("%2d ", ichan);
00598          TGo4Log::Info("%s", sInfoSaving.Data() );
00599          for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00600          {
00601             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00602                continue;
00603             sInfoSaving = Form("tdc #%2d: ",imodule );
00604             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00605             {
00606                if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00607                {
00608                fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00609                                                  TObject::kOverwrite);
00610                sInfoSaving += " 1 ";
00611                }
00612                   else sInfoSaving += " 0 ";
00613             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00614             TGo4Log::Info("%s", sInfoSaving.Data() );
00615          } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00616          //fileCalibrationOut->Write("",TObject::kOverwrite);
00617          fileCalibrationOut->Close();
00618          TGo4Log::Info("Calibration data saved in %s", sCalibOutFilename.Data() );
00619       } // if( kTRUE == fileCalibrationOut->IsOpen() )
00620          else TGo4Log::Warn("Error when deleting TVftxProc: Unable to open root file %s to save calibration data, please check settings",
00621                               sCalibOutFilename.Data() );
00622       gDirectory->Cd(oldDir->GetPath());
00623    } // if( 1 == fPar->uEnableCalibOutput && 1 == fPar->uEnableCalib )
00624    if( ( 1 == fPar->uSingleChannelCalibFilesOutput || 2 == fPar->uSingleChannelCalibFilesOutput )
00625          && 1 == fPar->uEnableCalib )
00626    {
00627       TString sInfoSaving = "Saved initial calibration histograms for following VFTX channels:";
00628       TGo4Log::Info("%s", sInfoSaving.Data() );
00629       sInfoSaving = "         ";
00630       for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00631          sInfoSaving += Form("%2d ", ichan);
00632       TGo4Log::Info("%s", sInfoSaving.Data() );
00633 
00634       oldDir = gDirectory;
00635       for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00636       {
00637          if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00638             continue;
00639          sInfoSaving = Form("tdc #%2d: ",imodule );
00640          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00641          {
00642             TString sCalibOutFilename = Form("./Calib/Tdc%02dChan%02d.root", imodule, ichan );
00643             TFile* fileCalibrationOut = new TFile( sCalibOutFilename, "RECREATE",
00644                                                   Form("Calibration Data for VFTX %02d channel %02d", imodule, ichan ),
00645                                                   9);
00646             if( kTRUE == fileCalibrationOut->IsOpen() )
00647             {
00648                sCalibOutFilename += ":/";
00649                gDirectory->Cd(sCalibOutFilename);
00650                if( 1 == fPar->uSingleChannelCalibFilesOutput || 0 == fInitialCalibHisto[imodule][ichan] )
00651                {
00652                   // New Calibration histo using only new data
00653                   if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00654                   {
00655                      fFineTime[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00656                                                        TObject::kOverwrite);
00657                      sInfoSaving += " 1 ";
00658                   } // if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00659                      else sInfoSaving += " 0 ";
00660                } // if( 1 == fPar->uSingleChannelCalibFilesOutput )
00661                else
00662                {
00663                   // Try to update old calibration histo with new data
00664                   if( 0 < (fFineTime[imodule][ichan]->GetEntries() ) )
00665                      fInitialCalibHisto[imodule][ichan]->Add( fFineTime[imodule][ichan] );
00666                   fInitialCalibHisto[imodule][ichan]->Write( Form("CalibHisto_tdc%02d_chan%02d", imodule, ichan),
00667                                                     TObject::kOverwrite);
00668                   sInfoSaving += " 1 ";
00669                } // else of if( 1 == fPar->uSingleChannelCalibFilesOutput )
00670             } // if( kTRUE == fileCalibrationOut->IsOpen() )
00671                else sInfoSaving += " 0 ";
00672             //fileCalibrationOut->Write("",TObject::kOverwrite);
00673             fileCalibrationOut->Close();
00674             gDirectory->Cd(oldDir->GetPath());
00675          } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00676          TGo4Log::Info("%s", sInfoSaving.Data() );
00677       } // for( Int_t imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00678       gDirectory->Cd(oldDir->GetPath());
00679    } // if( 1 == fPar->uSingleChannelCalibFilesOutput && 1 == fPar->uEnableCalib )
00680 }
00681 
00682 void TVftxProc::InitEvent(TGo4EventElement* outevnt)
00683 {
00684    // first assign input event:
00685    // since input event object is never discarded within processor lifetime,
00686    // we just search for subevent by name once to speed up processing
00687 
00688    //cout << "VftxProc Init Event " <<  endl;
00689 
00690    if(fCrateInputEvent==0)
00691    {
00692       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(GetInputEvent());
00693       if(btevent)
00694       {
00695          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(btevent->GetSubEvent("MBSCRATE"));
00696          if( kTRUE == fParAnalysis->bWithTriglog )
00697             fTriglogInputEvent=dynamic_cast<TTriglogEvent*>(btevent->GetSubEvent("TRIGLOG"));
00698       }
00699       else
00700       {
00701          fCrateInputEvent=dynamic_cast<TMbsCrateEvent*>(GetInputEvent());
00702       }
00703       if(fCrateInputEvent==0) {
00704         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event is not a TMbsCrateEvent!!! STOP GO4");
00705       }
00706       if(fTriglogInputEvent==0 && kTRUE == fParAnalysis->bWithTriglog ) {
00707         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: input event has no TTriglogEvent!!! STOP GO4");
00708       }
00709    }
00710    // then assign output event
00711 
00712    // since output event object is never discarded within processor lifetime,
00713    // we just search for subevent by name once to speed up processing
00714    if(fOutputEvent==0)
00715    {
00716       TCBMBeamtimeEvent* btevent=dynamic_cast<TCBMBeamtimeEvent*>(outevnt);
00717       if(btevent)
00718       {
00719          fOutputEvent=dynamic_cast<TVftxEvent*>(btevent->GetSubEvent("VFTX"));
00720       }
00721       else
00722       {
00723 
00724          fOutputEvent= dynamic_cast<TVftxEvent*>(outevnt);
00725       }
00726       if(fOutputEvent==0) {
00727         GO4_STOP_ANALYSIS_MESSAGE("**** TVftxProc: Fatal error: output event is not a TVftxEvent!!! STOP GO4");
00728       }
00729       else {
00730          //     BuildEvent(dynamic_cast<TGo4MbsSubEvent*>(btevent->GetSubEvent("MBSCRATE")));
00731       }
00732    }
00733 }
00734 
00735 void TVftxProc::FinalizeEvent()
00736 {
00737   //   cout << "**** TVftxProc: Finalize Event " << endl;
00738 
00739    if( -1 < fParAnalysis->iTriggerRejection && kTRUE == fParAnalysis->bWithTriglog)
00740        if( 1 == ((fTriglogInputEvent->fVulomTriggerPattern>>fParAnalysis->iTriggerRejection)&0x1 )  )
00741       {
00742           // The trigger Rejection is active and we have rejected trigger
00743          return;
00744       }
00745 
00746    if (fCrateInputEvent->IsValid()) 
00747    {
00748       // variables
00749       Int_t imodule = 0;
00750       Int_t iEvtSizeHeader1[MAX_FPGA_TDC];
00751       Int_t iEvtSizeHeader2[MAX_FPGA_TDC];
00752       for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++) 
00753       {
00754          for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++) 
00755          {
00756             iFirstTime[imodule][ichan]     = -1;
00757             iFirstCoarse[imodule][ichan]   = -1;
00758             iFirstFine[imodule][ichan]     = -1;
00759             dFirstTimecorr[imodule][ichan] = -1;
00760             dFirstFineTimecorr[imodule][ichan] = -1;
00761             iLastTime[imodule][ichan]    = 0;
00762             for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00763             {
00764                dTimeCorr[imodule][ichan][imul] = -1;
00765                dFineTimeCorr[imodule][ichan][imul] = -1;
00766             }
00767             uTotalMultiplicity[imodule][ichan]    = 0;
00768          }
00769          iTriggerTime[imodule] = 0;
00770       }
00771       imodule = 0;
00772       // fill histograms    
00773       for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++) {
00774          if( 0 == fPar->uVftxCalHistosEnabled[fpga] )
00775             continue;
00776 
00777          unsigned num_hits = fCrateInputEvent->fFPGA[fpga].size(); // per tdc
00778          imodule  = fpga;
00779          
00780          if( 0 == num_hits && 0 == fCrateInputEvent->fFPGAHEAD[fpga].size() ) // check if fpga data are there
00781             continue;
00782          iEvtSizeHeader1[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).nr_data;
00783          iEvtSizeHeader2[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_nd;
00784          iTriggerTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00785          headTime[imodule] = fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_ct;
00786          
00787          if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00788          {
00789             fEventSizeHeader1[imodule]->Fill( iEvtSizeHeader1[imodule] );
00790             fEventSizeHeader2[imodule]->Fill( iEvtSizeHeader2[imodule] );
00791             fTriggerType[imodule]->Fill(fCrateInputEvent->fFPGAHEAD[fpga].at(0).fpga_fifo_tt);
00792             fTriggerTime[imodule]->Fill( iTriggerTime[imodule] );
00793          } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00794          
00795          (fOutputEvent->fVftxBoards[imodule]).iTriggerTime = headTime[imodule];
00796          
00797          for(unsigned i = 0; i<num_hits; i++) 
00798          {
00799             uint32_t ichan =  fCrateInputEvent->fFPGA[fpga].at(i).ch_ix;
00800             uint32_t bFutureBit = fCrateInputEvent->fFPGA[fpga].at(i).future_bit;
00801             int32_t iCoarseCounter =  fCrateInputEvent->fFPGA[fpga].at(i).coarse_ct;
00802             int32_t iFineCounter =  fCrateInputEvent->fFPGA[fpga].at(i).ch_tim;
00803 
00804             // for given module add data
00805             Int_t channel=ichan; 
00806                
00807             if( (imodule >= 0) && (imodule < MAX_FPGA_TDC) && 
00808                 (channel >= 0) && (channel < FPGA_TDC_NBCHAN) )
00809             {
00810 
00811                if( ((fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] < TVftxBoardData::TVftxBoardData::MaxMult) )
00812                {
00813                   (fOutputEvent->fVftxBoards[imodule]).iFineTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]   = iFineCounter;
00814                   (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ] = iCoarseCounter;
00815                   (fOutputEvent->fVftxBoards[imodule]).uFutureBit[channel][ (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel] ]  = bFutureBit;
00816                   (fOutputEvent->fVftxBoards[imodule]).iMultiplicity[channel]++;
00817                }
00818                uTotalMultiplicity[imodule][channel]++;
00819             }
00820                else continue;
00821 
00822             //Calculation of non-linear Correction
00823             if( 0 == uInitialMbsTime )
00824             {
00825                uInitialMbsTime   = fTriglogInputEvent->fMbsTimeSecs;
00826                uInitialVulomSync = fTriglogInputEvent->fVulomSyncNumber;
00827             }
00828             if( 1 == fPar->uFineHistEnable )
00829             {
00830                if( 0 == fFineTime[imodule][ichan]->GetEntries() )
00831                   iNbHitsForCalib[imodule][ichan] = 0;
00832                   
00833                fFineTime[imodule][ichan]->Fill(iFineCounter);
00834                
00835                iNbHitsForCalib[imodule][ichan] ++;
00836                if( fPar->iMinNbHitsCalib == iNbHitsForCalib[imodule][ichan] )
00837                   TGo4Log::Info("FPGA TDC: Calibration data ok for module %d channel %d, after %d events", imodule, ichan, fTriglogInputEvent->fVulomSyncNumber - uInitialVulomSync);
00838             }
00839             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable )
00840                fFineTimeEvo[imodule][ichan]->Fill( UInt_t((fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/3600), iFineCounter);
00841 
00842             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uCoarseTimeHisto )
00843                fCoarseTime[imodule][ichan]->Fill(iCoarseCounter);
00844 
00845             if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00846             {
00847                for (uint16_t ibit = 0; ibit <= 9; ibit++) 
00848                   if ((iFineCounter >> ibit) & 0x1) bitcontrol[imodule][ichan]->Fill( ibit );
00849                for (uint16_t ibit = 0; ibit <= 15; ibit++) 
00850                   if ((iCoarseCounter >> ibit) & 0x1) bitcontrolCoarse[imodule][ichan]->Fill( ibit );
00851             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uBitControl )
00852 
00853             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00854             {
00855                fChanUsage[imodule]->Fill(ichan);
00856                if (bFutureBit) fChanFuture[imodule]->Fill(ichan);
00857             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00858 
00859             if (iLastTime[imodule][ichan])
00860             {
00861                if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
00862                   fChanDouble[imodule]->Fill(ichan);
00863             }
00864             else
00865             {
00866                iFirstCoarse[imodule][ichan] = iCoarseCounter;
00867                iFirstFine[imodule][ichan]   = iFineCounter;
00868                iFirstTime[imodule][ichan]   = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)
00869                                                + iFineCounter; // Modif PAL to re-add the coarse counter shift
00870             }
00871 
00872             iLastTime[imodule][ichan] = (iCoarseCounter<<TDC_FIFO_COARSE_CT_SHIFT)  + iFineCounter;
00873          } // for(unsigned i = 0; i<num_hits; i++)
00874             
00875       } // for (int fpga=0;fpga<MAX_FPGA_TDC;fpga++)
00876 
00877       if( 1 == fPar->uEnableCalib )
00878       {
00879          //define correction variables
00880          Bool_t bincontrol[TDC_FIFO_FINE_CT+1];
00881          Int_t iSum[MAX_FPGA_TDC][FPGA_TDC_NBCHAN];
00882         
00883          for(imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
00884          {
00885             if( 0 == fPar->uVftxCalHistosEnabled[imodule] )
00886                continue;
00887 
00888             for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
00889             {
00890                // cout<<" Test Corr Tdc "<<imodule<<" chan "<<ichan<<endl;
00891                if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]  &&
00892                    -1 <  fPar->iMinNbHitsCalib)
00893                {
00894                   if(// iNbHitsForCalib[imodule][ichan]< (2*fPar->iMinNbHitsCalib) ||
00895                     0 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00896                   {
00897                      fDnlCh[imodule][ichan]->Reset();
00898                      fDnlCorr[imodule][ichan]->Reset();
00899                      //set a the sum to zero before summing over all bins in one channel
00900                      iSum[imodule][ichan] = 0;
00901                      Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() );
00902                      
00903                      for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00904                      {
00905                         Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1));
00906                         //Looking for the used bins
00907                         if( iBinContent <= 0)
00908                         {
00909                            bincontrol[ibin] = kFALSE;
00910                         }
00911                         else if( iBinContent > 0)
00912                         {
00913                            bincontrol[ibin] = kTRUE;
00914                         }
00915                            
00916                         // build the sum of all bin content
00917                         if(bincontrol[ibin])
00918                         {
00919                 iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00920                 dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00921                 if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00922                     0 == iNbHitsForCalib[imodule][ichan]%10000 )
00923                   fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00924                               CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00925                         }else
00926                         {
00927                            if( 0 < ibin)
00928                               dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00929                               else dCorr[imodule][ichan][ibin]=0;
00930                         }      
00931                         fDnlCh[imodule][ichan]->Fill(ibin, (Double_t)iBinContent/dTotalEntriesInHisto );
00932                         fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00933                      } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00934                   } // if( iNbHitsForCalib[imodule][ichan]<1e6 || 0 == iNbHitsForCalib[imodule][ichan]%40000 )
00935                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
00936                   else if( -1 < fPar->iMinNbHitsCalib )
00937                   {
00938                      // Try to use initial calibration histo as long as under 
00939                      // the minimal number of hits in calibration
00940                      if( 0 != fInitialCalibHisto[imodule][ichan] &&
00941                          fPar->iMinNbHitsCalib - 1 == iNbHitsForCalib[imodule][ichan]%fPar->iMinNbHitsCalib )
00942                      {
00943                         fDnlCh[imodule][ichan]->Reset();
00944                         fDnlCorr[imodule][ichan]->Reset();
00945                         //set a the sum to zero before summing over all bins in one channel
00946                         iSum[imodule][ichan] = 0;
00947                         Double_t dTotalEntriesInHisto = (Double_t)(fFineTime[imodule][ichan]->GetEntries() ) + 
00948                                                         (Double_t)(fInitialCalibHisto[imodule][ichan]->GetEntries() );
00949                         
00950                         for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00951                         {
00952                            Int_t iBinContent = (Int_t)(fFineTime[imodule][ichan]->GetBinContent(ibin+1)) +
00953                                                (Int_t)(fInitialCalibHisto[imodule][ichan]->GetBinContent(ibin+1));
00954                            //Looking for the used bins
00955                            if( iBinContent <= 0)
00956                            {
00957                               bincontrol[ibin] = kFALSE;
00958                            }
00959                            else if( iBinContent > 0)
00960                            {
00961                               bincontrol[ibin] = kTRUE;
00962                            }
00963                               
00964                            // build the sum of all bin content
00965                            if(bincontrol[ibin])
00966                            {
00967                    iSum[imodule][ichan] = iSum[imodule][ichan] + iBinContent;
00968                    dCorr[imodule][ichan][ibin] = (Double_t)iSum[imodule][ichan] / dTotalEntriesInHisto;
00969                    if( 1 == fPar->uVftxCalHistosEnabled[imodule] && 1 == fPar->uFineEvolutionHistEnable && 
00970                          9999 == iNbHitsForCalib[imodule][ichan]%10000 )
00971                      fBinSizeEvo[imodule][ichan]->Fill( (Double_t)(fTriglogInputEvent->fMbsTimeSecs - uInitialMbsTime)/60.0, 
00972                                  CLOCK_TIME*(Double_t)(iBinContent) / dTotalEntriesInHisto );
00973                            }else
00974                            {
00975                               if( 0 < ibin)
00976                                  dCorr[imodule][ichan][ibin] = dCorr[imodule][ichan][ibin-1];
00977                                  else dCorr[imodule][ichan][ibin]=0;
00978                            }      
00979                            fDnlCh[imodule][ichan]->Fill(ibin, (Double_t)iBinContent/dTotalEntriesInHisto );
00980                            fDnlCorr[imodule][ichan]->Fill(ibin, dCorr[imodule][ichan][ibin] );               
00981                         } // for(Int_t ibin=0; ibin <= (Int_t)TDC_FIFO_FINE_CT; ibin++)
00982                      } //  if( 0 != fInitialCalibHisto[imodule][ichan] )
00983                   } // else of else if( -1 == fPar->iMinNbHitsCalib && 0 != fInitialCalibHisto[imodule][ichan])
00984                
00985                if( ( -1<fPar->iMinNbHitsCalib && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan]) ||
00986                    0 != fInitialCalibHisto[imodule][ichan] )
00987                {
00988                   if( 0<=iFirstCoarse[imodule][ichan] || 0<=iFirstFine[imodule][ichan] )
00989                   {
00990           dFirstTimecorr[imodule][ichan] = iFirstCoarse[imodule][ichan]*CLOCK_TIME
00991                    +  (1 - dCorr[imodule][ichan][iFirstFine[imodule][ichan]])*CLOCK_TIME;
00992                    dFirstFineTimecorr[imodule][ichan] = dCorr[imodule][ichan][iFirstFine[imodule][ichan]]*CLOCK_TIME;  
00993                   }  
00994                   for( Int_t imul = 0; imul< TVftxBoardData::MaxMult; imul++) 
00995                      if( 0<=(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul] || 
00996                          0<=(fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul])
00997                      {
00998                         dTimeCorr[imodule][ichan][imul] = (fOutputEvent->fVftxBoards[imodule]).iCoarseTime[ichan][imul]*CLOCK_TIME
00999                             +  (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME; 
01000                         dFineTimeCorr[imodule][ichan][imul] = (1 - dCorr[imodule][ichan][(fOutputEvent->fVftxBoards[imodule]).iFineTime[ichan][imul]])*CLOCK_TIME;
01001 
01002                         // Time offset correction
01003                         if( 1 == fPar->uEnableTimeOffsetCalibration  )
01004                         {
01005                            if( -1 < fPar->iVftxBoardIndex[imodule] )
01006                               dTimeCorr[imodule][ichan][imul] -=
01007                                     fPar->dTimeOffset[ fPar->iVftxBoardIndex[imodule] ][ (ichan - ichan%2 )/2];
01008                               else dTimeCorr[imodule][ichan][imul] -=
01009                                     fPar->dMeanTimeOffset[ (ichan - ichan%2 )/2 ];
01010                         } // if( 1 == fPar->uEnableTimeOffsetCalibration )
01011                         // Tot  offset correction, only for even channels (offset to the odd aka "time" channel)
01012                         if( 1 == fPar->uEnableTotCalibration && 0 == ichan%2 )
01013                         {
01014                            if( -1 < fPar->iVftxBoardIndex[imodule] )
01015                               dTimeCorr[imodule][ichan][imul] -= fPar->dTotOffset[ fPar->iVftxBoardIndex[imodule] ][ichan/2];
01016                               else dTimeCorr[imodule][ichan][imul] -= fPar->dMeanTotOffset[ichan/2];
01017                         } // if( 1 == fPar->uEnableTotCalibration && 0 == ichan%2 )
01018 
01019                         // Fill it in output event
01020                         (fOutputEvent->fVftxBoards[imodule]).dTimeCorr[ichan][imul]     = dTimeCorr[imodule][ichan][imul];
01021                         (fOutputEvent->fVftxBoards[imodule]).dFineTimeCorr[ichan][imul] = dFineTimeCorr[imodule][ichan][imul];
01022                      } // if( iFineTime ok || iCoarseTime ok)
01023                } // if( fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])
01024                
01025             } // for( Int_t ichan = 0; ichan< FPGA_TDC_NBCHAN; ichan++)
01026                
01027             //Compare corrected time with trigger time 
01028             if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
01029             {
01030 #if defined(VERSION_VFTX) || defined(VERSION_VFTX_28) // 1 TDC mode, chan = Time, chan +1 = Tot
01031                /*
01032                Double_t dTimeToTrigger[FPGA_TDC_NBCHAN];
01033                Double_t dToT[FPGA_TDC_NBCHAN];
01034                for( Int_t ichan = 0; ichan < FPGA_TDC_NBCHAN; ichan ++)
01035                {
01036                   if( 1 == fPar->uTimeHistEnable && 
01037                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] || 0 != fInitialCalibHisto[imodule][ichan])&&
01038                       0 < iFirstTime[imodule][ichan] )
01039                   {
01040                      dTimeToTrigger[ichan] = dFirstTimecorr[imodule][ichan] - iTriggerTime[imodule]*CLOCK_TIME;
01041                      if( VFTX_COARSE_OVERFLW_CHK < iFirstCoarse[imodule][ichan] - iTriggerTime[imodule])
01042                         dTimeToTrigger[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01043                      if( iFirstCoarse[imodule][ichan] - iTriggerTime[imodule] < -1*VFTX_COARSE_OVERFLW_CHK )
01044                         dTimeToTrigger[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01045                      fTime[imodule][ichan]->Fill( dTimeToTrigger[ichan] );
01046                   }
01047                   if( 1 == fPar->uTotHistoEnable && ichan < FPGA_TDC_NBCHAN/2 )
01048                      if( 0 < iFirstTime[imodule][ichan*2] && 0 < iFirstTime[imodule][ichan*2+1] &&
01049                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2]   || 0 != fInitialCalibHisto[imodule][ichan*2]  )&&
01050                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan*2+1] || 0 != fInitialCalibHisto[imodule][ichan*2+1]) )
01051                      {
01052                         dToT[ichan] =  dFirstTimecorr[imodule][ichan*2] -  dFirstTimecorr[imodule][ichan*2+1] ;
01053                         if( VFTX_COARSE_OVERFLW_CHK < iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] )
01054                            dToT[ichan] -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01055                         if( iFirstCoarse[imodule][ichan*2]- iFirstCoarse[imodule][ichan*2+1] < -1*VFTX_COARSE_OVERFLW_CHK )
01056                            dToT[ichan] += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01057                         fToT[imodule][ichan]->Fill(dToT[ichan]);
01058                      } // if( 1 == fPar->uTotHistoEnable && .... )
01059                }
01060                */
01061 #else
01062                if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][0])
01063                   fTime[imodule][0]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME - dFirstTimecorr[imodule][0]);
01064                if( 1 == fPar->uTotHistoEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0]
01065                   && fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
01066                   fToT[0]->Fill(((Double_t)iTriggerTime[0]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[0][0] 
01067                              - (((Double_t)iTriggerTime[1]*(Double_t)CLOCK_TIME ) -dFirstTimecorr[1][0]));
01068                Double_t dToT[FPGA_TDC_NBCHAN];
01069                for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
01070                {
01071                   if( 1 == fPar->uTimeHistEnable && fPar->iMinNbHitsCalib <= iNbHitsForCalib[imodule][ichan] )
01072                      fTime[imodule][ichan]->Fill( (iTriggerTime[imodule] +1 -headTime[imodule] )*CLOCK_TIME
01073                                                   - dFirstTimecorr[imodule][ichan]);
01074                   if( 1 == fPar->uTotHistoEnable && 
01075                       0 < iFirstTime[0][ichan] && 0 < iFirstTime[1][ichan] &&
01076                       0 < iFirstTime[0][0]     && 0 < iFirstTime[1][0]  && 
01077                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
01078                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][1] &&
01079                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[0][0] &&
01080                       fPar->iMinNbHitsCalib <= iNbHitsForCalib[1][0] )
01081                   {
01082                       dToT[ichan] = (iTriggerTime[0]*(Double_t)CLOCK_TIME )  - dFirstTimecorr[0][ichan] 
01083                         - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][ichan])
01084                         - ( (iTriggerTime[0]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[0][0] 
01085                        - ((iTriggerTime[1]*(Double_t)CLOCK_TIME ) - dFirstTimecorr[1][0])) ;
01086                      fToT[ichan]->Fill(dToT[ichan]);
01087                   } // if( 1 == fPar->uTotHistoEnable && .... )
01088                } // for( Int_t ichan = 1; ichan < FPGA_TDC_NBCHAN; ichan ++)
01089 #endif
01090             } // if( 1 == fPar->uVftxCalHistosEnabled[imodule] )
01091          } // for(  imodule = 0; imodule < MAX_FPGA_TDC; imodule ++)
01092 
01093          // Fill the output event
01094          for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
01095          {
01096             if( 0 == fPar->uVftxCalHistosEnabled[iModule] )
01097                continue;
01098 
01099             Double_t dTimeToTrigger;
01100             Double_t dToT;
01101             for(Int_t iChan=0; iChan < FPGA_TDC_NBCHAN; iChan++)
01102             {
01103                for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
01104                {
01105                   if( 1 == fPar->uTimeHistEnable &&
01106                       (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan] || 0 != fInitialCalibHisto[iModule][iChan])&&
01107                       0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]  )
01108                   {
01109                      dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
01110                                      - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01111                      if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01112                                                  - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01113                         dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01114                      if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01115                          - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01116                         dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01117                      fTime[iModule][iChan]->Fill( dTimeToTrigger );
01118 
01119                      if( 1 == fPar->uTimeHistSinglesEnable && 0 == iHit &&
01120                            1 == (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ])
01121                      {
01122                         Double_t dTimeToTriggerSingle =
01123                                           (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
01124                                         - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01125                         if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01126                                                     - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01127                            dTimeToTriggerSingle -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01128                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01129                             - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01130                            dTimeToTriggerSingle += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01131                         fTimeSingles[iModule][iChan]->Fill( dTimeToTriggerSingle );
01132                      }
01133 
01134                      if( 1 == fPar->uMultiHitsDistanceHistoEnable)
01135                         if( 0 < iHit && iHit < TVftxBoardData::MaxMult +1)
01136                            if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit] &&
01137                                 -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit - 1] )
01138                            {
01139                               Double_t dTimeToPreviousHit = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit]
01140                                                           - (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan][iHit - 1];
01141                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01142                                                           - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit - 1])
01143                                  dTimeToPreviousHit -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01144                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit]
01145                                 - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iHit - 1] < -1*VFTX_COARSE_OVERFLW_CHK )
01146                                  dTimeToPreviousHit += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01147                               fMultihitsDistance[iModule][iChan]->Fill( dTimeToPreviousHit, iHit);
01148                               if( 1 == iHit )
01149                                  fSecondHitDistance[iModule][iChan]->Fill(
01150                                      - (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan][1]
01151                                      + (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan][0],
01152                                        (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][1]
01153                                      - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][0]);
01154                            } // if( 0 < iHit && iHit < TVftxBoardData::MaxMult +1)
01155 /*
01156                      if( 6 == iModule && 32 == iChan )
01157                         fHitMergingTest10[1][iHit]->Fill(dTimeToTrigger);
01158                      if( 6 == iModule && 33 == iChan )
01159                         fHitMergingTest10[0][iHit]->Fill(dTimeToTrigger);
01160                         */
01161                   } // if hit is ok and calibrated
01162                } // for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan ]; iHit++)
01163 
01164                if( 1 == fPar->uTotHistoEnable && iChan < FPGA_TDC_NBCHAN/2 )
01165                {
01166                   for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2 ] &&
01167                                        iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2+1 ]; iHit++)
01168                   {
01169                      if( 0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit] &&
01170                            0 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit] &&
01171                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2]   || 0 != fInitialCalibHisto[iModule][iChan*2]  )&&
01172                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2+1] || 0 != fInitialCalibHisto[iModule][iChan*2+1]) )
01173                      {
01174                         dToT =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][iHit]
01175                                      -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][iHit];
01176                         if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
01177                                                     - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] )
01178                            dToT -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01179                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][iHit]
01180                             - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][iHit] < -1*VFTX_COARSE_OVERFLW_CHK )
01181                            dToT += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01182                         fToT[iModule][iChan]->Fill(dToT);
01183 /*
01184                         if( 6 == iModule && 16 == iChan )
01185                            fHitMergingTest9[iHit]->Fill(dToT);
01186                            */
01187                      } // if both edges ok and calibrated
01188                   } // for all hits until one edge is missing
01189                   /*
01190                   if( 2 <= (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2 ] &&
01191                       2 <= (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2+1 ] )
01192                      if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0] &&
01193                            -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0] &&
01194                            -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1] &&
01195                            -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1] &&
01196                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2]   || 0 != fInitialCalibHisto[iModule][iChan*2]  )&&
01197                         (fPar->iMinNbHitsCalib <= iNbHitsForCalib[iModule][iChan*2+1] || 0 != fInitialCalibHisto[iModule][iChan*2+1]) )
01198                      {
01199                         Double_t dToT1 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0]
01200                                      -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0];
01201                         if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01202                                                     - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] )
01203                            dToT1 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01204                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01205                             - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01206                            dToT1 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01207 
01208                         Double_t dToT2 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01209                                      -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1];
01210                         if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01211                                                     - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1] )
01212                            dToT2 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01213                         if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01214                             - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1] < -1*VFTX_COARSE_OVERFLW_CHK )
01215                            dToT2 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01216 
01217                         Double_t dTimeDiff1;
01218                         Double_t dTimeDiff2;
01219                         Double_t dTotDiff;
01220 
01221                         if( dToT1 < 0 && dToT2 < 0)
01222                         {
01223                            dTimeDiff1 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01224                                               -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0];
01225                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01226                                                        - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] )
01227                               dTimeDiff1 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01228                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01229                              - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01230                               dTimeDiff1 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01231 
01232                            dTimeDiff2 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01233                                               -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0];
01234                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01235                                                        - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] )
01236                               dTimeDiff2 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01237                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01238                              - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01239                               dTimeDiff2 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01240 
01241                            dTotDiff =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1]
01242                                              -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0];
01243                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01244                                                        - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] )
01245                               dTotDiff -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01246                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01247                              - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01248                               dTotDiff += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01249 
01250                            dToT1 *= -1;
01251                            dToT2 *= -1;
01252                         } // if( dToT1 < 0 && dToT2 < 0)
01253                            else
01254                            {
01255                               dTimeDiff1 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1]
01256                                                  -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0];
01257                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01258                                                           - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] )
01259                                  dTimeDiff1 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01260                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01261                                 - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01262                                  dTimeDiff1 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01263 
01264                               dTimeDiff2 =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1]
01265                                                  -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0];
01266                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01267                                                           - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] )
01268                                  dTimeDiff2 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01269                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01270                                 - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01271                                  dTimeDiff2 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01272 
01273                               dTotDiff =  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01274                                                 -  (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0];
01275                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01276                                                           - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] )
01277                                  dTotDiff -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01278                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01279                                 - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0] < -1*VFTX_COARSE_OVERFLW_CHK )
01280                                  dTotDiff += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01281                            } // else of if( dToT1 < 0 && dToT2 < 0)
01282 
01283                         fHitMergingTest[iModule][iChan]->Fill( dToT1, dTimeDiff1);
01284                         fHitMergingTest2[iModule][iChan]->Fill(dToT1, dTimeDiff2);
01285                         fHitMergingTest3[iModule][iChan]->Fill(dToT1, dTotDiff);
01286                         fHitMergingTest4[iModule][iChan]->Fill(dTimeDiff1, dTotDiff);
01287                         fHitMergingTest5[iModule][iChan]->Fill(dToT1, dToT2);
01288                         if( dTimeDiff2 <= 0)
01289                         {
01290                            fHitMergingTest6[iModule][iChan]->Fill(
01291                                  (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan*2+1][0],
01292                                  (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan*2+1][1]);
01293                            fHitMergingTest7[iModule][iChan]->Fill(
01294                                  (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan*2][0],
01295                                  (fOutputEvent->fVftxBoards[iModule]).iFineTime[iChan*2][1]);
01296                            fHitMergingTest8[iModule][iChan]->Fill(
01297                                  (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2+1 ],
01298                                  (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[ iChan*2 ]);
01299                            fHitMergingTest14[iModule][iChan]->Fill(
01300                                  (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01301                                - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0]);
01302                            fHitMergingTest15[iModule][iChan]->Fill(
01303                                  (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01304                                - (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]);
01305 
01306                            if( 6 == iModule && 16 == iChan )
01307                            {
01308                               dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0]
01309                                               - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01310                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01311                                                           - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01312                                  dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01313                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01314                                   - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01315                                  dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01316                               fHitMergingTest11[0]->Fill( dTimeToTrigger );
01317 
01318                               dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0]
01319                                               - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01320                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0]
01321                                                           - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01322                                  dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01323                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0]
01324                                   - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01325                                  dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01326                               fHitMergingTest11[1]->Fill( dTimeToTrigger );
01327 
01328                               dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01329                                               - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01330                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01331                                                           - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01332                                  dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01333                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01334                                   - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01335                                  dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01336                               fHitMergingTest11[2]->Fill( dTimeToTrigger );
01337 
01338                               dTimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1]
01339                                               - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01340                               if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01341                                                           - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01342                                  dTimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01343                               if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01344                                   - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01345                                  dTimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01346                               fHitMergingTest11[3]->Fill( dTimeToTrigger );
01347                            } // if( 6 == iModule && 16 == iChan )
01348                         } // if( dTimeDiff2 <= 0)
01349                         if( 6 == iModule && 16 == iChan )
01350                         {
01351                            Double_t dTimeToTrigger1 = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][0]
01352                                            - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01353                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01354                                                        - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01355                               dTimeToTrigger1 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01356                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][0]
01357                                - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01358                               dTimeToTrigger1 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01359 
01360                            Double_t dTimeToTrigger2 = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][0]
01361                                            - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01362                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0]
01363                                                        - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01364                               dTimeToTrigger2 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01365                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][0]
01366                                - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01367                               dTimeToTrigger2 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01368 
01369                            Double_t dTimeToTrigger3 = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2][1]
01370                                            - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01371                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01372                                                        - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01373                               dTimeToTrigger3 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01374                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2][1]
01375                                - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01376                               dTimeToTrigger3 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01377 
01378                            Double_t dTimeToTrigger4 = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[iChan*2+1][1]
01379                                            - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime*CLOCK_TIME;
01380                            if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01381                                                        - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime)
01382                               dTimeToTrigger4 -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01383                            if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan*2+1][1]
01384                                - (fOutputEvent->fVftxBoards[iModule]).iTriggerTime < -1*VFTX_COARSE_OVERFLW_CHK )
01385                               dTimeToTrigger4 += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01386 
01387                            if( -200000 < dTimeToTrigger4 && dTimeToTrigger4 < 180000)
01388                               fHitMergingTest12[0]->Fill(dTimeToTrigger2);
01389                            if( -190000 < dTimeToTrigger3 && dTimeToTrigger3 < 170000)
01390                               fHitMergingTest12[1]->Fill(dTimeToTrigger1);
01391 
01392                            fHitMergingTest13[0]->Fill(dTimeToTrigger2, dTimeToTrigger4);
01393                            fHitMergingTest13[1]->Fill(dTimeToTrigger1, dTimeToTrigger3);
01394                         } // if( 6 == iModule && 16 == iChan )
01395                      } // if More than 2 hits for both time and tot and all are ok
01396                      */
01397                } // if( 1 == fPar->uTotHistoEnable && iChan < FPGA_TDC_NBCHAN/2 )
01398 
01399                // Go back to index for VFTX internal map
01400                if( 1 == fPar->uVftxCoincidenceMap )
01401                   iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
01402                            - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2;
01403 
01404                if( 1 == fPar->uVftxCalHistosEnabled[iModule]  &&
01405                    0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan] )
01406                {
01407                   fChanEvents[iModule]->Fill(iChan);
01408                   if( 1 == fPar->uVftxCoincidenceMap )
01409                   {
01410                      if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01411                      {
01412                         TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
01413                               iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule);
01414                         return;
01415                      } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01416                      for(Int_t iChan2=iChan+1; iChan2<FPGA_TDC_NBCHAN; iChan2++)
01417                         if( 1 == fPar->uVftxCalHistosEnabled[iModule] && 0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[iChan2] )
01418                         {
01419                            fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
01420                         }
01421 
01422                      for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
01423                      {
01424                         // Find index for corresponding VFTX against VFTX map
01425                         iMapIndex = MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2
01426                                  - (MAX_FPGA_TDC-iModule)*((MAX_FPGA_TDC-iModule)+1)/2
01427                                  + (iModule2 - iModule);
01428                         if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01429                         {
01430                            TGo4Log::Info("****Vftx monitor: Error filling mapping histos: index out of boundary : %d / %d (tdc #%d VS tdc #%d)",
01431                                  iMapIndex, MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2, iModule, iModule2);
01432                            return;
01433                         } // if( MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 < iMapIndex )
01434                         for(Int_t iChan2=0; iChan2<FPGA_TDC_NBCHAN; iChan2++)
01435                            if( 1 == fPar->uVftxCalHistosEnabled[iModule2] && 0<(fOutputEvent->fVftxBoards[iModule2]).iMultiplicity[iChan2] )
01436                            {
01437                               fTdcChanStripMapping[ iMapIndex ]->Fill( iChan, iChan2 );
01438                            }
01439                      } // for(Int_t iModule2=iModule+1; iModule2<MAX_FPGA_TDC; iModule2++)
01440                   } // if( 1 == fPar->uVftxCoincidenceMap )
01441                } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && chan1 there)
01442 
01443                if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
01444                   fChanMultip[iModule]->Fill(iChan, uTotalMultiplicity[iModule][iChan] );
01445             } // for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++)
01446          } //  for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01447 
01448          // Checking how diamond time relatice to trigger depend on the triggers
01449          Double_t dRef2TimeToTrigger = 0.0;
01450          for(Int_t iTrigger = 0; iTrigger<16; iTrigger++)
01451             if( 1 == ((fTriglogInputEvent->fVulomTriggerPattern>>iTrigger) & 0x1) )
01452                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01453                   if( -1 < fPar->iVftxReference2Channel[iModule] )
01454                      for( Int_t iHit = 0; iHit < (fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference2Channel[iModule] ]; iHit++)
01455                {
01456                   dRef2TimeToTrigger = (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][iHit]
01457                                           - iTriggerTime[iModule]*CLOCK_TIME;
01458                   if( VFTX_COARSE_OVERFLW_CHK < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxReference2Channel[iModule]][iHit]
01459                                               - iTriggerTime[iModule])
01460                      dRef2TimeToTrigger -= ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01461                   if( (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[fPar->iVftxReference2Channel[iModule]][iHit]
01462                       - iTriggerTime[iModule] < -1*VFTX_COARSE_OVERFLW_CHK )
01463                      dRef2TimeToTrigger += ((TDC_FIFO_COARSE_CT>>TDC_FIFO_COARSE_CT_SHIFT)+1)*(Double_t)CLOCK_TIME;
01464                   fRef2TimeTriggerDep[iModule]->Fill( dRef2TimeToTrigger, iTrigger );
01465                } //  for Trigger, Module, Hit, if Trigger there and Diamond channel of the module defined
01466 
01467          if( -1 < iFirstModuleWithReference2)
01468             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] &&
01469                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).iMultiplicity[fPar->iVftxReference2Channel[iFirstModuleWithReference2]] )
01470                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01471                   if( iModule != iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01472                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference2Channel[iModule]] )
01473                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][0] &&
01474                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).dTimeCorr[fPar->iVftxReference2Channel[iFirstModuleWithReference2]][0] )
01475                      fTdcResolutionRef2Check[iModule]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference2Channel[iModule]][0] -
01476                                 (fOutputEvent->fVftxBoards[iFirstModuleWithReference2]).dTimeCorr[fPar->iVftxReference2Channel[iFirstModuleWithReference2]][0] );
01477 
01478          if( -1 < iFirstModuleWithReference1)
01479             if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] &&
01480                   0<(fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).iMultiplicity[fPar->iVftxReference1Channel[iFirstModuleWithReference1]] )
01481                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01482                   if( iModule != iFirstModuleWithReference1 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference1Channel[iModule] )
01483                   {
01484                      if(  0<(fOutputEvent->fVftxBoards[iModule]).iMultiplicity[fPar->iVftxReference1Channel[iModule]] )
01485                         if( -1 < (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference1Channel[iModule]][0] &&
01486                             -1 < (fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).dTimeCorr[fPar->iVftxReference1Channel[iFirstModuleWithReference1]][0] )
01487                      fTdcResolutionRef1Check[iModule]->Fill( (fOutputEvent->fVftxBoards[iModule]).dTimeCorr[fPar->iVftxReference1Channel[iModule]][0] -
01488                                 (fOutputEvent->fVftxBoards[iFirstModuleWithReference1]).dTimeCorr[fPar->iVftxReference1Channel[iFirstModuleWithReference1]][0] );
01489                   } // if( 1 == fPar->uVftxCalHistosEnabled[iModule] && fPar->iVftxReference1Channel[iModule] )
01490 
01491          // Automatic detection of the 1 clock cycle offset between TDcs due to
01492          // uncertainty on the exact reset time on startup
01493          if( 1 == fPar->uAutomaticOffsetEnable )
01494          {
01495             if( -1 < iFirstModuleWithReference1)
01496             {
01497                if( iFirstModuleWithReference1 == iFirstModuleWithReference2 &&
01498                    1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1])
01499                {
01500                   // Use both reference signals for more safety
01501                   for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01502                      if( 1 == fPar->uVftxCalHistosEnabled[iModule] && iModule != iFirstModuleWithReference1 &&
01503                          -1 < fPar->iVftxReference1Channel[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01504                         if( 5000 < ( fTdcResolutionRef1Check[iModule]->GetEntries() + fTdcResolutionRef2Check[iModule]->GetEntries() ) )
01505                         {
01506                            if( fTdcResolutionRef1Check[iModule]->GetMean() < - 2500 &&
01507                                fTdcResolutionRef2Check[iModule]->GetMean() < - 2500 )
01508                               fPar->iAutomaticTdcOffset[iModule] = 1;
01509                            else if( 2500 < fTdcResolutionRef1Check[iModule]->GetMean() &&
01510                                      2500 < fTdcResolutionRef2Check[iModule]->GetMean() )
01511                               fPar->iAutomaticTdcOffset[iModule] = -1;
01512                         } // if( 5000 < ( fTdcResolutionRef1Check[iModule-1]->GetEntries() + fTdcResolutionRef2Check[iModule-1]->GetEntries() ) )
01513                } // if( -1 < iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1])
01514                   else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01515                   {
01516                      // Check position of the peak in reference 1 signal difference between TDCs
01517                      for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01518                         if( iModule != iFirstModuleWithReference1 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference1Channel[iModule] )
01519                            if( 5000 < fTdcResolutionRef1Check[iModule]->GetEntries() )
01520                            {
01521                               if( fTdcResolutionRef1Check[iModule]->GetMean() < - 2500 )
01522                                  fPar->iAutomaticTdcOffset[iModule] = 1;
01523                               else if( 2500 < fTdcResolutionRef1Check[iModule]->GetMean() )
01524                                  fPar->iAutomaticTdcOffset[iModule] = -1;
01525                            } // if( 5000 < fTdcResolutionRef1Check[iModule-1]->GetEntries() )
01526                   } // else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01527             } // if( -1 < iFirstModuleWithReference1)
01528                else if( -1 < iFirstModuleWithReference2)
01529                {
01530                   if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference2] )
01531                   {
01532                      // Check position of the peak in reference 2 signal difference between TDCs
01533                      for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++)
01534                         if( iModule != iFirstModuleWithReference2 && 1 == fPar->uVftxCalHistosEnabled[iModule] && -1 < fPar->iVftxReference2Channel[iModule] )
01535                            if( 5000 < fTdcResolutionRef2Check[iModule]->GetEntries() )
01536                            {
01537                               if( fTdcResolutionRef2Check[iModule]->GetMean() < - 2500 )
01538                                  fPar->iAutomaticTdcOffset[iModule] = 1;
01539                               else if( 2500 < fTdcResolutionRef2Check[iModule]->GetMean() )
01540                                  fPar->iAutomaticTdcOffset[iModule] = -1;
01541                            } // if( 5000 < fTdcResolutionRef1Check[iModule-1]->GetEntries() )
01542                   } // else if(  1 == fPar->uVftxCalHistosEnabled[iFirstModuleWithReference1] )
01543                } // else if( -1 < iFirstModuleWithReference2) of if( -1 < iFirstModuleWithReference1)
01544          } // if( 1 == fPar->uAutomaticOffsetEnable )
01545 
01546          fOutputEvent->SetValid(kTRUE);
01547       } // if( 1 == fPar->uEnableCalib )
01548          else
01549          {
01550             if( 1 == fPar->uTimeHistEnable )
01551                for(Int_t iModule=0; iModule<MAX_FPGA_TDC; iModule++) 
01552                   if( 1 == fPar->uVftxCalHistosEnabled[iModule] )
01553                      for(Int_t iChan=0; iChan<FPGA_TDC_NBCHAN; iChan++) 
01554                         for( Int_t iMul = 0; iMul< TVftxBoardData::MaxMult; iMul++) 
01555                         { 
01556                            if( -1 < (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul] )
01557                               fTime[iModule][iChan]->Fill(
01558                                     (fOutputEvent->fVftxBoards[iModule]).iCoarseTime[iChan][iMul]
01559                                             - iTriggerTime[iModule]  );
01560                         }
01561          }// else of if( 1 == fPar->uEnableCalib )
01562       fOutputEvent->SetValid(kTRUE);
01563    } //  IsValid
01564    return;
01565 }