00001 #ifndef TVFTXPROC_H 00002 #define TVFTXPROC_H 00003 00004 #include "TGsiAug12Analysis.h" 00005 #include "TGsiAug12Param.h" 00006 00007 #include "TCBMBeamtimeProc.h" 00008 00009 #include "MBSUNPACK/TMbsCrateEvent.h" 00010 #include "TTriglogEvent.h" 00011 #include "TVftxEvent.h" 00012 #include "TVftxParam.h" 00013 #include "../../mbs/cbmvme.h" 00014 00015 00016 #include "TGo4Picture.h" 00017 #include "TH1.h" 00018 #include "TH2.h" 00019 00020 #include "TFile.h" 00021 #include "TTree.h" 00022 #include <fstream> 00023 #include <vector> 00024 00025 #define SYNCH_CHANNEl 0 00026 00027 class TGo4EventElement; 00028 class TGo4MbsSubEvent; 00029 00030 class TVftxProc : public TCBMBeamtimeProc { 00031 // friend class TCBMBeamtimeProc; 00032 public: 00033 TVftxProc(const char* name = 0); 00034 virtual ~TVftxProc(); 00035 virtual void InitEvent(TGo4EventElement*); 00036 virtual void FinalizeEvent(); 00037 private: 00038 00039 // for each FPGA TDC we have header information 00040 // for each FPGA TDC channel we have coarse time, fine time, and future bit 00041 // it is multi-hit tdc so we need additional index 00042 UInt_t event_nr; 00043 Int_t headTime[MAX_FPGA_TDC]; 00044 00045 Int_t iFirstTime[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00046 Int_t iFirstCoarse[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00047 Int_t iFirstFine[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00048 Int_t iLastTime[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00049 Int_t iLastToT[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00050 Int_t iTriggerTime[MAX_FPGA_TDC]; 00051 00052 Int_t iNbHitsForCalib[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00053 Double_t dCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TDC_FIFO_FINE_CT+1]; 00054 Double_t dFirstTimecorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00055 Double_t dFirstFineTimecorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00056 Double_t dTimeCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TVftxBoardData::MaxMult]; 00057 Double_t dFineTimeCorr[MAX_FPGA_TDC][FPGA_TDC_NBCHAN][TVftxBoardData::MaxMult]; 00058 00059 UInt_t uTotalMultiplicity[MAX_FPGA_TDC][FPGA_TDC_NBCHAN]; 00060 00061 TFile* fileCalibrationIn; 00062 TDirectory* oldDir; 00063 TH1 *fInitialCalibHisto[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00064 00065 TH1 *bitcontrol[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00066 TH1 *bitcontrolCoarse[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00067 TH1 *fEventSizeHeader1[MAX_FPGA_TDC]; 00068 TH1 *fEventSizeHeader2[MAX_FPGA_TDC]; 00069 TH1 *fTriggerType[MAX_FPGA_TDC]; 00070 TH1 *fTriggerTime[MAX_FPGA_TDC]; 00071 00072 TH1 *fChanUsage[MAX_FPGA_TDC]; 00073 TH1 *fChanEvents[MAX_FPGA_TDC]; 00074 TH1 *fChanDouble[MAX_FPGA_TDC]; 00075 TH1 *fChanFuture[MAX_FPGA_TDC]; 00076 00077 TH2 *fChanMultip[MAX_FPGA_TDC]; 00078 TH2 *fMultihitsDistance[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00079 TH2 *fSecondHitDistance[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00080 00081 TH1 *fTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00082 TH1 *fTimeSingles[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00083 TH1 *fToT[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00084 00085 TH1 *fFineTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00086 TH1 *fDnlCh[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00087 TH1 *fDnlCorr[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00088 TH1 *fCoarseTime[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00089 00090 TH2 *fFineTimeEvo[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00091 TH2 *fBinSizeEvo[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN ]; 00092 UInt_t uInitialMbsTime; 00093 UInt_t uInitialVulomSync; 00094 00095 TH2 *fTdcChanStripMapping[ MAX_FPGA_TDC*(MAX_FPGA_TDC+1)/2 ]; 00096 Int_t iMapIndex; 00097 00098 TH1 *fTdcResolutionRef2Check[MAX_FPGA_TDC]; 00099 Int_t iFirstModuleWithReference2; 00100 TH2 *fRef2TimeTriggerDep[MAX_FPGA_TDC]; 00101 00102 00103 TH1 *fTdcResolutionRef1Check[MAX_FPGA_TDC]; 00104 Int_t iFirstModuleWithReference1; 00105 /* 00106 TH2* fHitMergingTest[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00107 TH2* fHitMergingTest2[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00108 TH2* fHitMergingTest3[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00109 TH2* fHitMergingTest4[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00110 TH2* fHitMergingTest5[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00111 TH2* fHitMergingTest6[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00112 TH2* fHitMergingTest7[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00113 TH2* fHitMergingTest8[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00114 TH1* fHitMergingTest9[TVftxBoardData::MaxMult]; 00115 TH1* fHitMergingTest10[2][TVftxBoardData::MaxMult]; 00116 TH1* fHitMergingTest11[4]; 00117 TH1* fHitMergingTest12[2]; 00118 TH2* fHitMergingTest13[2]; 00119 TH1* fHitMergingTest14[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00120 TH1* fHitMergingTest15[MAX_FPGA_TDC][ FPGA_TDC_NBCHAN/2 ]; 00121 */ 00122 protected: 00123 00124 TVftxParam * fPar; 00125 TGsiAug12Param * fParAnalysis; 00126 TMbsCrateEvent * fCrateInputEvent; 00127 TVftxEvent * fOutputEvent; 00128 TTriglogEvent* fTriglogInputEvent; 00129 00130 protected: 00131 00132 ClassDef(TVftxProc,1) 00133 }; 00134 00135 #endif //TVFTXPROC_H 00136
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