(r4864/r890)

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Defines
#define	ROC_NX_HWV 0x400000
#define	ROC_NX_TESTPULSE_RESET_DELAY 0x403000
#define	ROC_NX_TESTPULSE_LENGTH 0x403004
#define	ROC_NX_TESTPULSE_LENGTH2 0x403008
#define	ROC_NX_TESTPULSE_NUMBER 0x40300C
#define	ROC_NX_TESTPULSE_START 0x403010
#define	ROC_NX_TESTPULSE_RUNNING 0x403014
#define	ROC_NX_NXACTIVE 0x402500
#define	ROC_NX_FEB4NX 0x402508
#define	ROC_NX_PARITY_CHECK 0x402504
#define	ROC_NX_I2C_RESET 0x410004
#define	ROC_NX_I2C_REGRESET 0x410008
#define	ROC_NX_ADC_DIRECT_1a 0x404200
#define	ROC_NX_ADC_DIRECT_1b 0x404204
#define	ROC_NX_ADC_DIRECT_1c 0x404208
#define	ROC_NX_ADC_DIRECT_1d 0x40420C
#define	ROC_NX_ADC_DIRECT_2a 0x404210
#define	ROC_NX_ADC_DIRECT_2b 0x404214
#define	ROC_NX_ADC_DIRECT_2c 0x404218
#define	ROC_NX_ADC_DIRECT_2d 0x40421C
#define	ROC_NX_ADC_REG 0x404000
#define	ROC_NX_ADC_ADDR 0x404004
#define	ROC_NX_ADC_ANSWER 0x404008
#define	ROC_NX_ADC_REG2 0x404100
#define	ROC_NX_ADC_ADDR2 0x404104
#define	ROC_NX_ADC_ANSWER2 0x404108
#define	ROC_NX_SR_INIT 0x402100
#define	ROC_NX_BUFG_SELECT 0x402104
#define	ROC_NX_SR_INIT2 0x402200
#define	ROC_NX_BUFG_SELECT2 0x402204
#define	ROC_NX_DELAY_LTS 0x402000
#define	ROC_NX_DELAY_NX0 0x402010
#define	ROC_NX_DELAY_NX1 0x402014
#define	ROC_NX_DELAY_NX2 0x402018
#define	ROC_NX_DELAY_NX3 0x40201C
#define	ROC_NX_ADC_LATENCY1 0x402300
#define	ROC_NX_ADC_LATENCY2 0x402304
#define	ROC_NX_ADC_LATENCY3 0x402308
#define	ROC_NX_ADC_LATENCY4 0x40230C
#define	ROC_NX_ADC_PORT_SELECT1 0x402400
#define	ROC_NX_ADC_PORT_SELECT2 0x402404
#define	ROC_NX_ADC_PORT_SELECT3 0x402408
#define	ROC_NX_ADC_PORT_SELECT4 0x40240C
#define	ROC_NX_DEBUG_MODE 0x402600
#define	ROC_NX_FIFO_EMPTY 0x401108
#define	ROC_NX_FIFO_FULL 0x40110C
#define	ROC_NX_LT_LOW 0x401000
#define	ROC_NX_LT_HIGH 0x401004
#define	ROC_NX_ADC_DATA 0x401100
#define	ROC_NX_NX_DATA 0x401104
#define	ADC_PORT_A 0
#define	ADC_PORT_B 1
#define	ADC_PORT_C 2
#define	ADC_PORT_D 3

Define Documentation

#define ADC_PORT_A 0

Definition at line 380 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::getAdcDirect().

#define ADC_PORT_B 1

Definition at line 381 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::getAdcDirect().

#define ADC_PORT_C 2

Definition at line 382 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::getAdcDirect().

#define ADC_PORT_D 3

Definition at line 383 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_ADDR 0x404004

{ROC, write-only, 8 bit} This register holds the device register address for the next SPI access to the main ADC on ROC port 0. Part of Main ADC control interface.

Definition at line 155 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getRegister(), and nxyter::MainAdc::setRegister().

#define ROC_NX_ADC_ADDR2 0x404104

{ROC, write-only, 8 bit} Like ROC_ADC_ADDR but for ROC port 1.

Part of Main ADC control interface.

Definition at line 176 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getRegister(), and nxyter::MainAdc::setRegister().

#define ROC_NX_ADC_ANSWER 0x404008

{ROC, read-only, 8 bit} A read from this register causes a SPI read transaction from the main ADC on ROC port 0. The device register given by ROC_ADC_ADDR is read and the retrieved data is made avaibale via ROC_ADC_ANSWER. Part of Main ADC control interface.

Definition at line 163 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getRegister(), and nxyter::MainAdc::setRegister().

#define ROC_NX_ADC_ANSWER2 0x404108

{ROC, read-only, 8 bit} Like ROC_ADC_ANSWER but for ROC port 1.

Part of Main ADC control interface.

Definition at line 182 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getRegister(), and nxyter::MainAdc::setRegister().

#define ROC_NX_ADC_DATA 0x401100

{ROC, read-only, 16 bit} Part of 'DAQ debug port' and can be used when ROC_DEBUG_MODE is set to 1 to access th 'wide FIFO'. The 'wide-FIFO' is implemented as three independent FIFO, to keep them consistent all three must be read, ROC_ADC_DATA, ROC_NX_DATA, and ROC_LT_LOW / ROC_LT_HIGH.

Detailed data format description in nxyter::DataDebug.

Part of DAQ interface.

Definition at line 367 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap().

#define ROC_NX_ADC_DIRECT_1a 0x404200

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 104 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_1b 0x404204

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 109 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_1c 0x404208

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 114 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_1d 0x40420C

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 119 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_2a 0x404210

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 124 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_2b 0x404214

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 129 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_2c 0x404218

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 134 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_DIRECT_2d 0x40421C

{ROC, read-only, 12 bit} Part of Main ADC data interface.

Definition at line 139 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::getAdcDirect().

#define ROC_NX_ADC_LATENCY1 0x402300

{ROC, read/write, 9 bit} Controls delay between ADC data capture (caused by 'frame clock edge'), and the association with the nXYTER data. Part of Main ADC data interface.

Definition at line 245 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getChannelLatency(), and nxyter::MainAdc::setChannelLatency().

#define ROC_NX_ADC_LATENCY2 0x402304

{ROC, read/write, 9 bit} Like ROC_ADC_LATENCY1 but for 2nd ADC channel. Part of Main ADC data interface.

Definition at line 250 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getChannelLatency(), and nxyter::MainAdc::setChannelLatency().

#define ROC_NX_ADC_LATENCY3 0x402308

{ROC, read/write, 9 bit} Like ROC_ADC_LATENCY1 but for 3rd ADC channel. Part of Main ADC data interface.

Definition at line 255 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getChannelLatency(), and nxyter::MainAdc::setChannelLatency().

#define ROC_NX_ADC_LATENCY4 0x40230C

{ROC, read/write, 9 bit} Like ROC_ADC_LATENCY1 but for 4th ADC channel. Part of Main ADC data interface.

Definition at line 260 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getChannelLatency(), and nxyter::MainAdc::setChannelLatency().

#define ROC_NX_ADC_PORT_SELECT1 0x402400

{ROC, read/write, 2 bit} Selects the ADC channel for the nXYTER with nXYTER number = 0. Possible values are:

0 use data from pin A17/B17
1 use data from pin A18/B18
2 use data from pin A20/B20
3 use data from pin A21/B21

Part of Main ADC data interface.

Note:: nXYTER number = 0 data come from CON19 if ROC_FEB4NX = 0 and from CON20 if ROC_FEB4NX = 1.

Definition at line 274 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setChannelMux().

#define ROC_NX_ADC_PORT_SELECT2 0x402404

{ROC, read/write, 2 bit} Like ROC_ADC_PORT_SELECT1 but for nXYTER with nXYTER number = 1. Part of Main ADC data interface.

Note:: nXYTER number = 1 data come from CON19 if ROC_FEB4NX = 0 and from CON20 if ROC_FEB4NX = 1.

Definition at line 282 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setChannelMux().

#define ROC_NX_ADC_PORT_SELECT3 0x402408

{ROC, read/write, 2 bit} Like ROC_ADC_PORT_SELECT1 but for nXYTER with nXYTER number = 2. Part of Main ADC data interface.

Note:: nXYTER number = 2 data always come from CON20.

Definition at line 289 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setChannelMux().

#define ROC_NX_ADC_PORT_SELECT4 0x40240C

{ROC, read/write, 2 bit} Like ROC_ADC_PORT_SELECT1 but for nXYTER with nXYTER number = 3. Part of Main ADC data interface.

Note:: nXYTER number = 3 data always come from CON20.

Definition at line 296 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setChannelMux().

#define ROC_NX_ADC_REG 0x404000

{ROC, write-only, 8 bit} A write into this register causes a SPI write transaction to the main ADC on ROC port 0. The device register given by ROC_ADC_ADDR is loaded with the data written into ROC_ADC_REG.

Part of Main ADC control interface.

Definition at line 149 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setRegister().

#define ROC_NX_ADC_REG2 0x404100

{ROC, write-only, 8 bit} Like ROC_ADC_REG but for ROC port 1.

Part of Main ADC control interface.

Definition at line 170 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), and nxyter::MainAdc::setRegister().

#define ROC_NX_BUFG_SELECT 0x402104

{ROC, read/write, ? bit} Part of Main ADC data interface.

Note:: For FEB4nx class the timing is deterimed with this parameter because the clocks are on port 0 (CON19).

Definition at line 197 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getClockDelayBufg(), and nxyter::MainAdc::setClockDelayBufg().

#define ROC_NX_BUFG_SELECT2 0x402204

{ROC, read/write, ? bit} Part of Main ADC data interface.

Definition at line 207 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getClockDelayBufg(), and nxyter::MainAdc::setClockDelayBufg().

#define ROC_NX_DEBUG_MODE 0x402600

{ROC, write-only, 1 bit} Controls whether the DAQ subsystem is working in normal mode (bit 0 is 0) or in 'debug' mode (bit 0 is 1). In debug mode the hit builder logic between 'wide FIFO' and 'event FIFO' is disabled and data can be read directly from the 'wide FIFO' via the registers ROC_NX_ADC_DATA, ROC_NX_NX_DATA, ROC_NX_LT_LOW, and ROC_NX_LT_HIGH.

Part of DAQ interface.

Definition at line 307 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::setDebugMode().

#define ROC_NX_DELAY_LTS 0x402000

{ROC, read/write, ? bit} Part of nXYTER data interface.

Definition at line 213 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), cmd_board(), and nxyter::RocNx::setLTSDelay().

#define ROC_NX_DELAY_NX0 0x402010

{ROC, read/write, 16 bit} Controls the delay of the RESET pulse for the FEB connected to port 0 (CON19) in units of 250 MHz clock cycles (4ns).

Part of nXYTER data interface.

Definition at line 220 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), nxyter::NxChip::getChannelDelay(), and nxyter::NxChip::setChannelDelay().

#define ROC_NX_DELAY_NX1 0x402014

{ROC, read/write, 16 bit} This 16 bit register is implemented but has no hardware function. It does despite its name it does not control any nXYTER timing !

See also:: ROC_DELAY_NX3.

Definition at line 226 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), nxyter::NxChip::getChannelDelay(), and nxyter::NxChip::setChannelDelay().

#define ROC_NX_DELAY_NX2 0x402018

{ROC, read/write, 16 bit} Controls the delay of the RESET pulse for the FEB connected to port 1 (CON20) in units of 250 MHz clock cycles (4ns). Part of nXYTER data interface.

Definition at line 232 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), nxyter::NxChip::getChannelDelay(), and nxyter::NxChip::setChannelDelay().

#define ROC_NX_DELAY_NX3 0x40201C

{ROC, read/write, 16 bit} This 16 bit register is implemented but has no hardware function. It does despite its name does not not control any nXYTER timing !

See also:: ROC_DELAY_NX1.

Definition at line 238 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), nxyter::NxChip::getChannelDelay(), and nxyter::NxChip::setChannelDelay().

#define ROC_NX_FEB4NX 0x402508

{ROC, read/write, 1 bit} If set to 1 the ROC is configured for a single FEB of .FEB4nx class Part of nXYTER data interface.

Definition at line 78 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::FebBase::initRoc().

#define ROC_NX_FIFO_EMPTY 0x401108

{ROC, read-only, 1 bit} A 1 indicates that of the the 3 FIFOs (NX, ADC, LTS) are empty.

Part of DAQ interface.

Definition at line 315 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::getFifoEmpty().

#define ROC_NX_FIFO_FULL 0x40110C

{ROC, read-only, 1 bit} A 1 indicates that of the the 3 FIFOs (NX, ADC, LTS) are full.

Part of DAQ interface.

Definition at line 322 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::getFifoFull().

#define ROC_NX_HWV 0x400000

{ROC, read-only, 32 bit} This register return version of nXYTER firmware block

Definition at line 7 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), cmd_printid(), cmd_printroc(), UdpSimulator::GetReg(), RocNxWidget::getSubConfig(), RocMainWidget::getSubConfig(), and UdpSimulator::PutReg().

#define ROC_NX_I2C_REGRESET 0x410008

{ROC, write-only, 1 bit} ACTIVE LOW! Part of nXYTER control interface.

Definition at line 98 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), UdpSimulator::PutReg(), and nxyter::FebBase::resetNxI2cRegister().

#define ROC_NX_I2C_RESET 0x410004

{ROC, write-only, 1 bit} ACTIVE LOW! Part of nXYTER control interface.

Definition at line 93 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), UdpSimulator::PutReg(), and nxyter::FebBase::resetNxI2cBus().

#define ROC_NX_LT_HIGH 0x401004

{ROC, read-only, 32 bit} Part of 'DAQ debug port' and can be used when ROC_DEBUG_MODE is set to 1 to access th 'wide FIFO'. The 'wide-FIFO' is implemented as three independent FIFO, to keep them consistent all three must be read, ROC_ADC_DATA, ROC_NX_DATA, and ROC_LT_LOW / ROC_LT_HIGH. The timestamp part is 64 bit and accessed via two registers, ROC_LT_LOW and ROC_LT_HIGH. Always read ROC_LT_LOW before ROC_LT_HIGH. The read access of ROC_LT_HIGH will advance the timestamp FIFO.

Note: ROC_LT_HIGH/ROC_LT_LOW reflect the internal 64 bit ROC local timestamp counter. Only the lower 44 bit are used in the message building, the 12 LSB's to decide on the 'last-epoch' bit, and the bits 43:12 to build the epoch marker (using a 32 bit epoch number).

Detailed data format description in nxyter::DataDebug.

Part of DAQ interface.

Definition at line 355 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap().

#define ROC_NX_LT_LOW 0x401000

{ROC, read-only, 32 bit} Part of 'DAQ debug port' and can be used when ROC_DEBUG_MODE is set to 1 to access th 'wide FIFO'. The 'wide-FIFO' is implemented as three independent FIFO, to keep them consistent all three must be read, ROC_ADC_DATA, ROC_NX_DATA, and ROC_LT_LOW / ROC_LT_HIGH. The timestamp part is 64 bit and accessed via two registers, ROC_LT_LOW and ROC_LT_HIGH. Always read ROC_LT_LOW before ROC_LT_HIGH.

Detailed data format description in nxyter::DataDebug.

Part of DAQ interface.

Definition at line 336 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap().

#define ROC_NX_NX_DATA 0x401104

{ROC, read-only, 32 bit} Part of 'DAQ debug port' and can be used when ROC_DEBUG_MODE is set to 1 to access th 'wide FIFO'. The 'wide-FIFO' is implemented as three independent FIFO, to keep them consistent all three must be read, ROC_ADC_DATA, ROC_NX_DATA, and ROC_LT_LOW / ROC_LT_HIGH.

Detailed data format description in nxyter::DataDebug.

Part of DAQ interface.

Definition at line 378 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap().

#define ROC_NX_NXACTIVE 0x402500

{ROC, read/write, 4 bit} Holds a mask with enable flags for the 4 nXYTER. A 0 mask bit will disable the recognition of data valid from the nXYTER and thus suppress generation of hits. Bit n corresponds to the nXYTER with the nXYTER number of n. Note that the red nXYTER activity LED on the ROC is controlled by the accepted hits and therefore affected by the setting of ROC_NX_ACTIVE. Part of nXYTER data interface.

Definition at line 72 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), nxyter::RocNx::getNxActive(), UdpSimulator::PutReg(), and nxyter::RocNx::setNxActive().

#define ROC_NX_PARITY_CHECK 0x402504

{ROC, read/write, 1 bit} If set to 1, the parity bit of nXYTER hits is checked. In case of a parity mismatch, the nXYTER hit is discarted and a nXYTER parity system message generated instead. If set to 0, no parity checking is performed, all nXYTER hits caused by a data valid will produce a hit message. Part of nXYTER data interface.

Definition at line 87 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), RocNxWidget::getSubConfig(), RocNxWidget::parityChanged(), nxyter::RocNx::setParityCheck(), and RocNxWidget::setSubConfig().

#define ROC_NX_SR_INIT 0x402100

{ROC, read/write, ? bit} Part of Main ADC data interface.

Note:: For FEB4nx class the timing is deterimed with this parameter because the clocks are on port 0 (CON19).

Definition at line 190 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getClockDelaySrInit(), and nxyter::MainAdc::setClockDelaySrInit().

#define ROC_NX_SR_INIT2 0x402200

{ROC, read/write, ? bit} Part of Main ADC data interface.

Definition at line 202 of file defines_nxyter.h.

Referenced by nxyter::MainAdc::addAddrMap(), nxyter::MainAdc::getClockDelaySrInit(), and nxyter::MainAdc::setClockDelaySrInit().

#define ROC_NX_TESTPULSE_LENGTH 0x403004

{ROC, write-only, 24 bit} This registers determines the length of time the test pulse is "H" (time between raising and falling edges). The "H" time is (LENGTH+1)*4 ns.

Part of ROC test pulser interface.

Definition at line 24 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::fireTestPulse().

#define ROC_NX_TESTPULSE_LENGTH2 0x403008

{ROC, write-only, 24 bit} This registers determines the length of time the test pulse is "L" (time between falling and rising edges). The "L" time is (LENGTH2+1)*4 ns.

Part of ROC test pulser interface.

Definition at line 32 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::fireTestPulse().

#define ROC_NX_TESTPULSE_NUMBER 0x40300C

{ROC, write-only, 16 bit} This register controls the number of edges to be generated after a start with ROC_TESTPULSE_START. Note, it is the number of edges, the number of pulses is half this count because test triggers/pulses are only generated on one edge.

Best is to only write even numbers into this register.

A setting of 0 will produce a continuous train of test pulses. To stop such a continuous sequence simply start a finite sequence, e.g. with a length of one. Part of ROC test pulser interface.

Definition at line 46 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::fireTestPulse().

#define ROC_NX_TESTPULSE_RESET_DELAY 0x403000

{ROC, write-only, 16 bit} This register determines the delay between the reset of the the ROC and nXYTER timestamp counters and the first raising edge of a test pulse. The delay is 4 ns per count. Part of ROC test pulser interface.

Definition at line 16 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::fireTestPulse().

#define ROC_NX_TESTPULSE_RUNNING 0x403014

{ROC, read-only} On read it returns the 'test pulser active' signal. 1 means a test pulse sequence is running, 0 means test pulse generator is not active. Part of ROC test pulser interface.

Definition at line 60 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap().

#define ROC_NX_TESTPULSE_START 0x403010

{ROC, write-only, function} A write will start the test pulser and produce a pulse train defined by the parameters loaded into ROC_TESTPULSE_RESET_DELAY, ROC_TESTPULSE_LENGTH, and ROC_TESTPULSE_NUMBER. Part of ROC test pulser interface.

Definition at line 53 of file defines_nxyter.h.

Referenced by nxyter::RocNx::addAddrMap(), and nxyter::RocNx::fireTestPulse().

include/nxyter/defines_nxyter.h File Reference

(r4864/r890)

Defines

Define Documentation